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    ADAPTIVE COMMON MODE BIAS FOR DIFFERENTIAL AMPLIFIER INPUT CIRCUITS
    1.
    发明申请
    ADAPTIVE COMMON MODE BIAS FOR DIFFERENTIAL AMPLIFIER INPUT CIRCUITS 有权
    用于差分放大器输入电路的自适应通用模式偏置

    公开(公告)号：US20110057727A1

    公开(公告)日：2011-03-10

    申请号：US12557139

    申请日：2009-09-10

    申请人： Hayden C. Cranford, JR. ,  Todd M. Rasmus ,  Joseph M. Stevens

    发明人： Hayden C. Cranford, JR. ,  Todd M. Rasmus ,  Joseph M. Stevens

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45183 ,  H03F1/3211 ,  H03F3/45632 ,  H03F2203/45008 ,  H03F2203/45078 ,  H03F2203/45292 ,  H03F2203/45342

    摘要： A method and apparatus for extending the common mode range of a differential amplifier. A circuit has a common mode detection circuit, a common mode voltage inversion circuit, and a differential amplifier. The common mode detection circuit receives a differential signal and detects a common mode voltage. The common mode voltage inversion circuit is coupled to the common mode detection circuit. The common mode voltage inversion circuit has an input node that receives the common mode voltage and an output node that outputs body voltage, wherein the common mode voltage inversion circuit creates an inverse relationship between the common mode voltage and the body voltage. The differential amplifier includes a differential pair of transistors that have a pair of body terminals coupled to the output node of the common mode voltage inversion circuit.

    摘要翻译： 一种用于扩展差分放大器的共模范围的方法和装置。 电路具有共模检测电路，共模电压反相电路和差分放大器。 共模检测电路接收差分信号并检测共模电压。 共模电压反相电路耦合到共模检测电路。 共模电压反相电路具有接收共模电压的输入节点和输出体电压的输出节点，其中共模电压反相电路在共模电压和体电压之间产生反向关系。 差分放大器包括具有耦合到共模电压反相电路的输出节点的一对主体端子的差分对晶体管。

    SYSTEM AND CIRCUIT FOR DETERMINING DATA SIGNAL JITTER VIA ASYNCHRONOUS SAMPLING
    2.
    发明申请
    SYSTEM AND CIRCUIT FOR DETERMINING DATA SIGNAL JITTER VIA ASYNCHRONOUS SAMPLING 有权
    用于通过异步采样确定数据信号抖动的系统和电路

    公开(公告)号：US20100030503A1

    公开(公告)日：2010-02-04

    申请号：US12103689

    申请日：2008-04-15

    申请人： Hayden C. Cranford, JR. ,  Fadi H. Gebara ,  Jeremy D. Schaub

    发明人： Hayden C. Cranford, JR. ,  Fadi H. Gebara ,  Jeremy D. Schaub

    IPC分类号： G06F19/00 ,  G06F17/18

    CPC分类号： G01R31/31725 ,  G01R29/26 ,  G01R31/31709 ,  H04L1/205

    摘要： A system and circuit for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are collected in a histogram according to a folding of the samples around a timebase. The timebase is determined by sweeping to detect a minimum jitter for the folded data. The histogram for the correct estimated timebase period is representative of the probability density function of the location of data signal edges and the jitter characteristics are determined by the width and shape of the density function peaks. Frequency drift can be corrected by adjusting the timebase used to fold the data across the sample set.

    摘要翻译： 用于通过异步采样确定数据信号抖动的系统和电路提供了用于测量数据信号抖动的低成本和生产可集成机制。 数据信号被边缘检测并通过不相关频率的采样时钟采样，采样值根据时基上的样本的折叠而被收集在直方图中。 通过扫描确定时基以检测折叠数据的最小抖动。 正确的估计时基周期的直方图代表数据信号边缘位置的概率密度函数，抖动特性由密度函数峰的宽度和形状决定。 可以通过调整用于在整个样本集中折叠数据的时基来纠正频率漂移。

    SERIAL LINK RECEIVER FOR HANDLING HIGH SPEED TRANSMISSIONS
    4.
    发明申请
    SERIAL LINK RECEIVER FOR HANDLING HIGH SPEED TRANSMISSIONS 有权
    串行接收器用于处理高速传输

    公开(公告)号：US20130064326A1

    公开(公告)日：2013-03-14

    申请号：US13228512

    申请日：2011-09-09

    申请人： Minhan Chen ,  Hayden C. Cranford, JR.

    发明人： Minhan Chen ,  Hayden C. Cranford, JR.

    IPC分类号： H04L27/00

    CPC分类号： H04L25/0276 ,  H04L25/0298

    摘要： A serial link receiver comprises first and second input terminals for receiving positive and negative inputs of a serial data signal, first and second broadband matching T-coils coupled to the first and second input terminals, first and second AC/DC coupling networks coupled to the first and second broadband matching T-coils, and a common mode level shifter coupled to the outputs from the first and second AC/DC coupling networks. This receiver architecture combines the ability to have a wide bandwidth input and pass through data signals at both low and high frequencies. This AC and DC coupled front end also incorporates the feature of a common mode level shifting network to place the common mode of the signal at the optimum point for the first active amplifier stage.

    摘要翻译： 串行链路接收机包括用于接收串行数据信号的正和负输入的第一和第二输入端，耦合到第一和第二输入端的第一和第二宽带匹配T型线圈，耦合到第一和第二AC / DC耦合网络 第一和第二宽带匹配T型线圈，以及耦合到来自第一和第二AC / DC耦合网络的输出的共模电平移位器。 该接收机架构结合了具有宽带宽输入和通过低频和高频数据信号的能力。 该AC和DC耦合前端还结合了共模电平转换网络的特征，以将信号的共模放置在第一有源放大器级的最佳点。

    Adaptive Noise Suppression Using a Noise Look-up Table
    5.
    发明申请
    Adaptive Noise Suppression Using a Noise Look-up Table 有权
    使用噪声查找表的自适应噪声抑制

    公开(公告)号：US20100031067A1

    公开(公告)日：2010-02-04

    申请号：US12183099

    申请日：2008-07-31

    申请人： Igor Arsovski ,  Hayden C. Cranford, JR. ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Hayden C. Cranford, JR. ,  Sebastian T. Ventrone

    IPC分类号： G06F1/03

    CPC分类号： G06F1/03 ,  G06F1/26

    摘要： A proactive noise suppression system and method for a power supply network of an integrated circuit. The system and method include receiving an IC event sequence to a memory element, correlating the IC event sequence to a storage location in a second memory element, the storage location including an anti-noise response signature, and utilizing the anti-noise response signature to proactively generate an anti-noise response in a power supply network in at least a portion of the integrated circuit at about the time of execution of the first IC event sequence. Anti-noise response signatures may be adaptively updated and/or created based on noise measurements made corresponding to execution of an IC event sequence by the integrated circuit.

    摘要翻译： 一种用于集成电路的电源网络的主动噪声抑制系统和方法。 该系统和方法包括：向存储元件接收IC事件序列，将IC事件序列与第二存储器元件中的存储位置相关联，存储位置包括抗噪声响应签名，并将抗噪声响应签名 在执行第一IC事件序列时，在集成电路的至少一部分中，主动地在电力供应网络中产生抗噪声响应。 基于通过集成电路执行IC事件序列进行的噪声测量可以自适应地更新和/或创建抗噪声响应签名。

    Structure for transmitter bandwidth optimization circuit
    6.
    发明申请
    Structure for transmitter bandwidth optimization circuit 有权
    发射机带宽优化电路的结构

    公开(公告)号：US20090129485A1

    公开(公告)日：2009-05-21

    申请号：US11985963

    申请日：2007-11-19

    申请人： Louis L. Hsu ,  Hayden C. Cranford, JR. ,  Joseph Natonio ,  James D. Rockrohr ,  Huihao Xu ,  Steven J. Zier

    发明人： Louis L. Hsu ,  Hayden C. Cranford, JR. ,  Joseph Natonio ,  James D. Rockrohr ,  Huihao Xu ,  Steven J. Zier

    IPC分类号： H04B3/00 ,  H04L27/00

    CPC分类号： H04L25/0286 ,  H04L25/03343

    摘要： A design structure embodied in a machine-readable medium used in a design process provides a transmitter having a frequency response controllable in accordance with an operational parameter, and may include a storage operable to store operational parameters for controlling a frequency response of the transmitter under each of a plurality of corresponding operating conditions. A sensor can be used to detect an operating condition. In response to a change in the detected operating condition, a stored operational parameter corresponding to the detected operating condition can be used to control the frequency response of the transmitter.

    摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构提供具有根据操作参数可控的频率响应的发射机，并且可以包括可操作地存储用于控制每个发射机的频率响应的操作参数的存储器 的多个相应的操作条件。 可以使用传感器来检测操作状态。 响应于检测到的操作条件的变化，可以使用与检测到的操作条件对应的存储的操作参数来控制发送器的频率响应。

    VARIABLE GAIN AMPLIFIER WITH REDUCED POWER CONSUMPTION
    8.
    发明申请
    VARIABLE GAIN AMPLIFIER WITH REDUCED POWER CONSUMPTION 有权
    具有降低功耗的可变增益放大器

    公开(公告)号：US20120001691A1

    公开(公告)日：2012-01-05

    申请号：US12828238

    申请日：2010-06-30

    申请人： Jieming Qi ,  David W. Boerstler ,  Minhan Chen ,  Hayden C. Cranford, JR.

    发明人： Jieming Qi ,  David W. Boerstler ,  Minhan Chen ,  Hayden C. Cranford, JR.

    IPC分类号： H03F3/45

    CPC分类号： H03G3/004 ,  H03F1/0205 ,  H03F3/189 ,  H03F3/45632 ,  H03F2200/294 ,  H03F2200/555 ,  H03F2203/45418

    摘要： A variable gain amplifier includes a first common mode (CM) node configured to receive a first differential signal of a pair of differential signals. A first regulator couples to the first CM node, the first regulator being configured to generate a first CM offset. A second CM node is configured to receive a second differential signal of the pair of differential signals. A second regulator couples to the second CM node, the second regulator being configured to generate a second CM offset. In one embodiment, the first CM offset and the second CM offset together comprise a net CM offset, the net CM offset being configured to replace a current source net offset.

    摘要翻译： 可变增益放大器包括被配置为接收一对差分信号的第一差分信号的第一共模（CM）节点。 第一调节器耦合到第一CM节点，第一调节器被配置为生成第一CM偏移。 第二CM节点被配置为接收该对差分信号的第二差分信号。 第二调节器耦合到第二CM节点，第二调节器被配置为生成第二CM偏移。 在一个实施例中，第一CM偏移和第二CM偏移量一起包括净CM偏移，净CM偏移被配置为替换当前源净偏移。

    Design structure for on-chip electromigration monitoring system
    9.
    发明申请
    Design structure for on-chip electromigration monitoring system 有权
    片上电迁移监控系统的设计结构

    公开(公告)号：US20090132985A1

    公开(公告)日：2009-05-21

    申请号：US11985966

    申请日：2007-11-19

    申请人： Louis L. Hsu ,  Hayden C. Cranford, JR. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

    发明人： Louis L. Hsu ,  Hayden C. Cranford, JR. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G01R31/2858

    摘要： A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to output a plurality of reference voltages having different values. A plurality of comparators in the semiconductor chip may be coupled to receive the reference voltages and a monitored voltage representative of a resistance of the monitored element. Each of the comparators may produce an output indicating whether the monitored voltage exceeds the reference voltages, so that the resistance value of the monitored element may be precisely determined.

    摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构可以包括半导体芯片的装置，其可操作以检测半导体芯片的被监测元件的电阻的增加。 该设计结构可以包括例如可操作以输出具有不同值的多个参考电压的电阻分压器电路。 可以将半导体芯片中的多个比较器耦合以接收参考电压和表示所监视元件的电阻的监视电压。 每个比较器可以产生指示监视的电压是否超过参考电压的输出，使得可以精确地确定被监视元件的电阻值。