公开(公告)号：US07027352B2

公开(公告)日：2006-04-11

申请号：US10635740

申请日：2003-08-05

申请人： Hea-Suk Jung

发明人： Hea-Suk Jung

IPC分类号： G11C8/00

CPC分类号： H03L7/0805 ,  H03L7/0814

摘要： A delay locked loop (DLL) in a semiconductor device, includes an clock buffer receiving an external clock signal and an inverted clock signal and outputting first and second internal clock signals to be used in the DLL circuit; and a variable clock divider receiving the second internal signal from the clock buffer and variably dividing the second internal clock signal to have a predetermined pulse width according to a control signal based on a column address strobe (CAS) latency, which is set according to a frequency of the external clock signal, wherein the control signal is initially set to have a first logic level and is enabled to a second logic level when the CAS latency corresponds to a high frequency.

摘要翻译： 半导体器件中的延迟锁定环（DLL）包括接收外部时钟信号和反相时钟信号的时钟缓冲器，并输出要在DLL电路中使用的第一和第二内部时钟信号; 以及可变时钟分频器，从时钟缓冲器接收第二内部信号，并且根据基于列地址选通（CAS）等待时间的控制信号，可变地将第二内部时钟信号划分为具有预定的脉冲宽度，该延迟是根据 所述外部时钟信号的频率，其中所述控制信号被初始设置为具有第一逻辑电平，并且当所述CAS等待时间对应于高频时，所述第二逻辑电平被使能到第二逻辑电平。

公开(公告)号：US07082179B2

公开(公告)日：2006-07-25

申请号：US10735336

申请日：2003-12-12

申请人： Hea-Suk Jung

发明人： Hea-Suk Jung

IPC分类号： H03K21/00

CPC分类号： H03L7/0805 ,  H03K23/58 ,  H03L7/0814 ,  H03L7/089

摘要： A divider of a DLL(delay locked loop) measures tAC for various periods due to variation of process, temperature and a supply voltage and provides a divided clock having an optimum tAC. The clock divider includes a clock dividing unit, a test mode clock providing unit and a normal mode clock providing unit. The clock dividing unit receives a source clock of the DLL to generate a plurality of divided clocks, each having a period different from each other. The test mode clock providing unit selectively outputs the plurality of the divided clocks in a test mode in response to a test mode signal and a test mode period selecting signal. And, the normal mode clock providing unit outputs selected one of the plurality of the divided clocks in a normal mode in response to the test mode signal.

摘要翻译： DLL（延迟锁定环）的分频器由于过程，温度和电源电压的变化而测量各种周期的tAC，并且提供具有最佳tAC的分频时钟。 时钟分频器包括时钟分频单元，测试模式时钟提供单元和正常模式时钟提供单元。 时钟分割单元接收DLL的源时钟以产生多个具有彼此不同的周期的分割时钟。 测试模式时钟提供单元响应于测试模式信号和测试模式周期选择信号，以测试模式选择性地输出多个划分的时钟。 并且，正常模式时钟提供单元响应于测试模式信号以正常模式输出所选择的多个分频时钟之一。

公开(公告)号：US20050122796A1

公开(公告)日：2005-06-09

申请号：US10876426

申请日：2004-06-25

申请人： Hea-Suk Jung ,  Jong-Tae Kwak

发明人： Hea-Suk Jung ,  Jong-Tae Kwak

IPC分类号： G11C11/407 ,  G11C7/00 ,  G11C7/10 ,  H03L7/081

CPC分类号： H03L7/0814 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0805

摘要： A delayed locked loop in a semiconductor memory device includes a read enable signal generating block for generating a read enable signal, wherein the read enable signal is enabled based on the application of a read command, and is disabled when all data is read out and outputted; a first internal clock controlling block for intermitting the output of a first internal clock through the use of the read enable signal; a second internal clock controlling block for intermitting the output of a second internal clock through the use of the read enable signal; a DLL clock generating block for receiving the first and second internal clocks to thereby generate first and second DLL clocks.

摘要翻译： 半导体存储器件中的延迟锁定环包括用于产生读使能信号的读使能信号产生块，其中读使能信号根据读命令的应用被使能，并且当所有数据被读出并输出时被禁止 ; 第一内部时钟控制块，用于通过使用读使能信号来中断第一内部时钟的输出; 第二内部时钟控制块，用于通过使用读使能信号来中断第二内部时钟的输出; DLL时钟产生块，用于接收第一和第二内部时钟，从而产生第一和第二DLL时钟。

公开(公告)号：US06342796B2

公开(公告)日：2002-01-29

申请号：US09742276

申请日：2000-12-19

申请人： Hea-Suk Jung

发明人： Hea-Suk Jung

IPC分类号： H03L700

CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A delay locked loop (DLL) for use in a synchronous memory device includes: a first shift controller for generating a first shift-right signal in response to a first comparison signal; a first shift register for performing only a shift-right operation in response to the first shift-right signal; a first delay line unit for controlling each delay amount of internal signals in response to an output of the first shift register, wherein the first delay line unit includes a plurality of delay lines, each delay line having a first unit delay; a second shift controller for generating a second shift-right signal and a shift-left signal in response to a second comparison signal; a second shift register for performing a shift-right operation and a shift-left operation in response to the second shift-right signal and the shift-left signal, respectively; and a second delay line unit for controlling each delay amount of output signals of the first delay line means, wherein the second delay line unit includes a plurality of delay lines, each delay line having a second unit delay smaller than the first unit delay.

摘要翻译： 用于同步存储器件的延迟锁定环（DLL）包括：第一移位控制器，用于响应于第一比较信号产生第一右移信号; 第一移位寄存器，用于仅响应于第一右移信号执行右移操作; 第一延迟线单元，用于响应于第一移位寄存器的输出来控制每个延迟量的内部信号，其中第一延迟线单元包括多个延迟线，每个延迟线具有第一单位延迟; 第二移位控制器，用于响应于第二比较信号产生第二右移信号和左移信号; 第二移位寄存器，用于分别响应于第二右移信号和左移信号执行右移操作和左移操作; 以及第二延迟线单元，用于控制第一延迟线装置的输出信号的每个延迟量，其中第二延迟线单元包括多个延迟线，每个延迟线具有小于第一单位延迟的第二单位延迟。

公开(公告)号：US07103133B2

公开(公告)日：2006-09-05

申请号：US10223434

申请日：2002-08-19

申请人： Hea-Suk Jung

发明人： Hea-Suk Jung

IPC分类号： H03D3/24 ,  H03L7/06

CPC分类号： H03L7/0805 ,  H03L7/0814 ,  H03L7/10

摘要： A register controlled delay locked loop (DLL) includes a clock divider, a shift controller, a delay unit and a delay model to synchronize an external clock signal with an internal clock. The register controlled DLL further includes a reset signal generator to generate a reset signal used to initialize the delay locked loop (DLL), a phase comparator to initialize a phase comparison signal in which the phase of a feedback clock signal delayed by a reference clock signal and the delay model is compared and outputted into a predetermined signal by using a comparison enable signal having an inverse phase to that of the reset signal, and a shift register to block an electric current running on a first latch of a plurality of latches with the reset signal during the initialization.

公开(公告)号：US20050017777A1

公开(公告)日：2005-01-27

申请号：US10735336

申请日：2003-12-12

申请人： Hea-Suk Jung

发明人： Hea-Suk Jung

IPC分类号： H03L7/00 ,  H03K23/58 ,  H03L7/081 ,  H03L7/089 ,  H03K21/00

CPC分类号： H03L7/0805 ,  H03K23/58 ,  H03L7/0814 ,  H03L7/089

摘要： A divider of a DLL(delay locked loop) measures tAC for various periods due to variation of process, temperature and a supply voltage and provides a divided clock having an optimum tAC. The clock divider includes a clock dividing unit, a test mode clock providing unit and a normal mode clock providing unit. The clock dividing unit receives a source clock of the DLL to generate a plurality of divided clocks, each having a period different from each other. The test mode clock providing unit selectively outputs the plurality of the divided clocks in a test mode in response to a test mode signal and a test mode period selecting signal. And, the normal mode clock providing unit outputs selected one of the plurality of the divided clocks in a normal mode in response to the test mode signal.

摘要翻译： DLL（延迟锁定环）的分频器由于过程，温度和电源电压的变化而测量各种周期的tAC，并且提供具有最佳tAC的分频时钟。 时钟分频器包括时钟分频单元，测试模式时钟提供单元和正常模式时钟提供单元。 时钟分割单元接收DLL的源时钟以产生多个具有彼此不同的周期的分割时钟。 测试模式时钟提供单元响应于测试模式信号和测试模式周期选择信号，以测试模式选择性地输出多个划分的时钟。 并且，正常模式时钟提供单元响应于测试模式信号以正常模式输出所选择的多个分频时钟之一。

公开(公告)号：US06593786B2

公开(公告)日：2003-07-15

申请号：US10180528

申请日：2002-06-27

申请人： Hea-Suk Jung

发明人： Hea-Suk Jung

IPC分类号： H03L706

CPC分类号： H03L7/0805 ,  H03L7/0814

摘要： A delay locked loop (DLL) usable in a semiconductor memory device and capable of reducing current consumption by operating the DLL loop when the semiconductor device is only at an operation mode, is provided. The semiconductor device includes a clock divider for producing a divided clock signal by dividing an internal clock signal, synchronized with an edge of an external clock signal; a clock generator for producing a reference clock signal, wherein the reference clock signal is activated after a half period of the external clock signal; a delay model for delaying the divided clock signal to compensate for a delay time in delay paths of the internal clock signal; a comparator for comparing a phase difference between the reference clock signal and an output signal from the delay model; a delay unit having a plurality of unit delayers; and a controller for controlling an amount of delay in the internal clock signal and the divided clock signal via the delay unit in response to a phase comparison signal from the comparator.

摘要翻译： 提供了一种可用于半导体存储器件并且当半导体器件仅处于操作模式时能够通过操作DLL环路来减少电流消耗的延迟锁定环（DLL）。 半导体器件包括时钟分频器，用于通过与内部时钟信号进行分频来产生分频时钟信号，该内部时钟信号与外部时钟信号的边沿同步; 用于产生参考时钟信号的时钟发生器，其中所述参考时钟信号在所述外部时钟信号的半周期之后被激活; 用于延迟分频时钟信号以补偿内部时钟信号的延迟路径中的延迟时间的延迟模型; 比较器，用于比较参考时钟信号和来自延迟模型的输出信号之间的相位差; 具有多个单位延迟器的延迟单元; 以及控制器，用于响应于来自比较器的相位比较信号，经由延迟单元控制内部时钟信号和分频时钟信号的延迟量。

公开(公告)号：US06433597B1

公开(公告)日：2002-08-13

申请号：US09896519

申请日：2001-06-29

申请人： Hea-Suk Jung

发明人： Hea-Suk Jung

IPC分类号： H03D324

摘要： A delay locked loop is disclosed which is less responsive to noise so as to improve an AC parameter tAC. The delay locked loop generally includes: a phase detector, a shift register, and a noise determining circuit which is enabled when the delay locked loop is locked for controlling driving of the shift register by determining whether a phase comparison signal from the phase detector is produced by noise. The noise determining circuit drives the shift register when the phase comparison signal has information for driving the shift register at least three times sequentially.