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    1T-1R architecture for resistive random access memory
    3.
    发明授权
    1T-1R architecture for resistive random access memory 有权

    公开(公告)号：US11152062B2

    公开(公告)日：2021-10-19

    申请号：US17008505

    申请日：2020-08-31

    申请人： HEFEI RELIANCE MEMORY LIMITED

    发明人： Deepak Chandra Sekar ,  Wayne Frederick Ellis

    IPC分类号： G11C13/00 ,  G11C5/06 ,  G11C5/02 ,  G11C11/419 ,  G11C11/16

    摘要： A memory device comprises: an array of memory cells arranged in a plurality of columns in a first direction and a plurality of rows in a second direction, wherein each memory cell in the array comprises: a select transistor, wherein a source terminal of the select transistor is coupled to a source line, and wherein a gate terminal of the select transistor is coupled to a word line, and a memory element coupled in series with the select transistor, wherein a first end of the memory element is coupled to a drain terminal of the select transistor, and wherein a second end of the memory element is coupled to a bit line; and a control circuit configured to provide an unselected source line voltage to source lines of unselected memory cells before providing a selected word line voltage to a word line of a selected memory cell.

    2T-1R architecture for resistive RAM
    8.
    发明授权
    2T-1R architecture for resistive RAM 有权

    公开(公告)号：US11081176B2

    公开(公告)日：2021-08-03

    申请号：US16796428

    申请日：2020-02-20

    申请人： Hefei Reliance Memory Limited

    发明人： Deepak Chandra Sekar ,  Wayne Frederick Ellis ,  Brent Steven Haukness ,  Gary Bela Bronner ,  Thomas Vogelsang

    IPC分类号： G11C13/00 ,  G11C7/08 ,  G11C8/10

    摘要： Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.