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    Vertical SOI trench SONOS cell
    8.
    发明授权
    Vertical SOI trench SONOS cell 有权
    垂直SOI沟槽SONOS单元

    公开(公告)号：US07514323B2

    公开(公告)日：2009-04-07

    申请号：US11164513

    申请日：2005-11-28

    申请人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    发明人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    IPC分类号： H01L29/00

    CPC分类号： H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

    摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

    摘要翻译： 提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取 基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

    Controlled recrystallization of buried strap in a semiconductor memory device
    9.
    发明授权
    Controlled recrystallization of buried strap in a semiconductor memory device 失效
    半导体存储器件中埋置带的可控再结晶

    公开(公告)号：US5543348A

    公开(公告)日：1996-08-06

    申请号：US412442

    申请日：1995-03-29

    申请人： Erwin Hammerl ,  Jack A. Mandelman ,  Herbert L. Ho ,  Junichi Shiozawa ,  Reinhard J. Stengl

    发明人： Erwin Hammerl ,  Jack A. Mandelman ,  Herbert L. Ho ,  Junichi Shiozawa ,  Reinhard J. Stengl

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10861

    摘要： A method of forming a coupled capacitor and transistor is provided. A trench is formed in a semiconductor substrate and an impurity-doped first conductive region is then formed by filling the trench with an impurity-doped first conductive material. The impurity-doped first conductive region is etched back to a first level within the trench. An insulating layer is then formed on a sidewall of the portion of the trench opened by the etching back of the impurity-doped first conductive region and a second conductive region is formed by filling the remainder of the trench with a second conductive material. The insulating layer and the second conductive region are etched back to a second level within the trench and an amorphous silicon layer is formed in the portion of the trench opened by the etching back of the insulating layer and the second conductive region. The undoped amorphous silicon layer is etched back to a third a level within the trench. The undoped amorphous silicon layer is then recrystallized. Impurities are outdiffused from the impurity-doped first conductive region to the semiconductor substrate through the recrystallized silicon layer. A source/drain region of the transistor is formed adjacent to an intersection of the trench and the surface of the semiconductor substrate. The outdiffused impurities and the recrystallized silicon layer constitute a buried strap for electrically connecting the first and second conductive layers in the trench to the source/drain region.

    摘要翻译： 提供一种形成耦合电容器和晶体管的方法。 在半导体衬底中形成沟槽，然后通过用杂质掺杂的第一导电材料填充沟槽来形成杂质掺杂的第一导电区域。 杂质掺杂的第一导电区域被回蚀刻到沟槽内的第一水平。 然后在通过杂质掺杂的第一导电区域的蚀刻开口的沟槽部分的侧壁上形成绝缘层，并且通过用第二导电材料填充沟槽的其余部分形成第二导电区域。 将绝缘层和第二导电区域回蚀刻到沟槽内的第二层，并且在通过绝缘层和第二导电区域的蚀刻打开的沟槽部分中形成非晶硅层。 未掺杂的非晶硅层在沟槽内回蚀刻到第三级。 然后将未掺杂的非晶硅层重结晶。 杂质通过再结晶硅层从杂质掺杂的第一导电区向外延伸到半导体衬底。 晶体管的源极/漏极区域形成为与沟槽和半导体衬底的表面的交点相邻。 超扩散杂质和再结晶硅层构成用于将沟槽中的第一和第二导电层电连接到源极/漏极区域的掩埋带。

    Vertical SOI trench SONOS cell
    10.
    发明授权
    Vertical SOI trench SONOS cell 有权
    垂直SOI沟槽SONOS单元

    公开(公告)号：US08008713B2

    公开(公告)日：2011-08-30

    申请号：US12410935

    申请日：2009-03-25

    申请人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    发明人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    IPC分类号： H01L29/00

    CPC分类号： H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

    摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

    摘要翻译： 提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取 基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。