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公开(公告)号：US07397684B2
公开(公告)日：2008-07-08
申请号：US11226447
申请日：2005-09-15
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G06F13/1668
摘要： A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and address signals connected with the memory controller, directly connecting at least one semiconductor memory chip with the memory controller and serially connecting with each other the semiconductor memory chips among each other by 1-point-to-1-point connections.
摘要翻译： 一种用于在具有用于存储用户数据的至少一个半导体存储器芯片和用于控制至少一个半导体存储器芯片的一个存储器控制器的数据存储系统中操作的半导体存储器阵列包括至少一个用于控制的单向串行信号线总线 以及与存储器控制器连接的地址信号，将至少一个半导体存储器芯片与存储器控制器直接连接，并且通过1点到1点连接彼此串联连接半导体存储器芯片。
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公开(公告)号：US20070058408A1
公开(公告)日：2007-03-15
申请号：US11226447
申请日：2005-09-15
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G06F13/1668
摘要： A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and address signals connected with the memory controller, directly connecting at least one semiconductor memory chip with the memory controller and serially connecting with each other the semiconductor memory chips among each other by 1-point-to-1-point connections.
摘要翻译： 一种用于在具有用于存储用户数据的至少一个半导体存储器芯片和用于控制至少一个半导体存储器芯片的一个存储器控制器的数据存储系统中操作的半导体存储器阵列包括至少一个用于控制的单向串行信号线总线 以及与存储器控制器连接的地址信号，将至少一个半导体存储器芯片与存储器控制器直接连接，并且通过1点到1点连接彼此串联连接半导体存储器芯片。
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3.发明申请公开(公告)号：US20070058409A1
公开(公告)日：2007-03-15
申请号：US11226448
申请日：2005-09-15
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： A semiconductor memory arrangement for operation in a data memory system with at least one semiconductor memory chip for the storage of user data includes a memory controller for control of the at least one semiconductor memory chip, and at least one unidirectional signal line bus for control and address signals connected with the memory controller and branching at least once. The at least once branching bus directly connecting at least one semiconductor memory chip with the memory controller and connecting the semiconductor memory chips among each other.
摘要翻译： 一种用于在具有用于存储用户数据的至少一个半导体存储器芯片的数据存储器系统中操作的半导体存储器装置包括用于控制至少一个半导体存储器芯片的存储器控制器和用于控制的至少一个单向信号线总线， 与存储器控制器连接的地址信号并至少分支一次。 所述至少一次分支总线将至少一个半导体存储器芯片与存储器控制器直接连接并将半导体存储器芯片彼此连接。
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4.发明授权公开(公告)号：US07411843B2
公开(公告)日：2008-08-12
申请号：US11226448
申请日：2005-09-15
IPC分类号： G11C7/00
CPC分类号： G11C5/063
摘要： A semiconductor memory arrangement for operation in a data memory system with at least one semiconductor memory chip for the storage of user data includes a memory controller for control of the at least one semiconductor memory chip, and at least one unidirectional signal line bus for control and address signals connected with the memory controller and branching at least once. The at least once branching bus directly connecting at least one semiconductor memory chip with the memory controller and connecting the semiconductor memory chips among each other.
摘要翻译： 一种用于在具有用于存储用户数据的至少一个半导体存储器芯片的数据存储器系统中操作的半导体存储器装置包括用于控制至少一个半导体存储器芯片的存储器控制器和用于控制的至少一个单向信号线总线， 与存储器控制器连接的地址信号并至少分支一次。 所述至少一次分支总线将至少一个半导体存储器芯片与存储器控制器直接连接并将半导体存储器芯片彼此连接。
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5.发明申请公开(公告)号：US20100074038A1
公开(公告)日：2010-03-25
申请号：US12234312
申请日：2008-09-19
申请人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
发明人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
IPC分类号： G11C7/10 , H01L21/66 , H01L23/538
CPC分类号： G11C7/1048 , G11C7/1006 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C29/70 , H01L2224/16145
摘要： A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.
摘要翻译： 公开了包括存储器阵列，存储器阵列数据终端和包括第一子总线和第二子总线的数据总线的存储器管芯。 还公开了布置在存储器阵列数据终端和第一子总线之间的第一双向缓冲器和布置在存储器阵列数据终端和第二副总线之间的第二双向缓冲器。 第一和第二双向缓冲器一次适于将第一子总线或第二子总线耦合到存储器阵列数据终端。
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6.发明授权公开(公告)号：US07796446B2
公开(公告)日：2010-09-14
申请号：US12234312
申请日：2008-09-19
申请人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
发明人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
IPC分类号： G11C7/10
CPC分类号： G11C7/1048 , G11C7/1006 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C29/70 , H01L2224/16145
摘要： A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.
摘要翻译： 公开了包括存储器阵列，存储器阵列数据终端和包括第一子总线和第二子总线的数据总线的存储器管芯。 还公开了布置在存储器阵列数据终端和第一子总线之间的第一双向缓冲器和布置在存储器阵列数据终端和第二副总线之间的第二双向缓冲器。 第一和第二双向缓冲器一次适于将第一子总线或第二子总线耦合到存储器阵列数据终端。
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7.发明授权Distributed command and address bus architecture for a memory module having portions of bus lines separately disposed 有权用于具有单独布置的总线线路的部分的存储器模块的分布式命令和地址总线架构公开(公告)号：US08161219B2
公开(公告)日：2012-04-17
申请号：US12328690
申请日：2008-12-04
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gärtner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gärtner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
IPC分类号： G06F13/00
CPC分类号： G06F13/409
摘要： Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions.
摘要翻译： 描述了内存模块和电路板的分布式命令和地址总线架构。 在一个实施例中，存储器模块包括设置在电路板边缘上的多个连接器引脚，所述多个连接器引脚包括耦合到多个数据总线的第一引脚，耦合到多个命令和地址总线的第二引脚 线，其中第二引脚设置在第一和第二区域中，其中第一引脚的一部分设置在第一和第二区域之间。
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公开(公告)号：US07848153B2
公开(公告)日：2010-12-07
申请号：US12194414
申请日：2008-08-19
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
IPC分类号： G11C16/06
CPC分类号： G11C11/4097 , G11C5/025 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks.
摘要翻译： 公开了存储器件和存储器模块。 在一个实施例中，存储器件包括具有第一边缘和与第一边缘相对的第二边缘的半导体衬底。 多个存储体设置在半导体衬底的中心部分，每个存储体包括多个存储单元。 多个输入/输出触点设置在第一边缘和存储体之间。 延迟锁定环电路设置在第一边缘附近。 多个地址和命令触点设置在第二边缘和存储体之间。
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公开(公告)号：US20100046266A1
公开(公告)日：2010-02-25
申请号：US12194414
申请日：2008-08-19
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
CPC分类号： G11C11/4097 , G11C5/025 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks.
摘要翻译： 公开了存储器件和存储器模块。 在一个实施例中，存储器件包括具有第一边缘和与第一边缘相对的第二边缘的半导体衬底。 多个存储体设置在半导体衬底的中心部分，每个存储体包括多个存储单元。 多个输入/输出触点设置在第一边缘和存储体之间。 延迟锁定环电路设置在第一边缘附近。 多个地址和命令触点设置在第二边缘和存储体之间。
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公开(公告)号：US20100032820A1
公开(公告)日：2010-02-11
申请号：US12187183
申请日：2008-08-06
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/49811 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/18 , H01L2224/0554 , H01L2224/05554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06572 , H01L2924/00014 , H01L2924/01055 , H01L2924/14 , H01L2924/3011 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/0555 , H01L2224/0556
摘要： Memory modules, computing systems, and methods of manufacturing memory modules are disclosed. In one embodiment, a memory module includes a substrate having a first side and a second side opposed to the first side. A plurality of pins is disposed on the first side of the substrate. A first plurality of memory chips are arranged in a first chip layer, the first chip layer overlying the second side of the substrate. Electrical contacts of the first plurality of memory chips are electrically coupled to the pins. A second plurality of memory chips is arranged in a second chip layer, the second chip layer overlying the first chip layer. Electrical contacts of the second plurality of memory chips are electrically coupled to the pins.
摘要翻译： 公开了内存模块，计算系统和制造内存模块的方法。 在一个实施例中，存储器模块包括具有与第一侧相对的第一侧和第二侧的衬底。 多个引脚设置在基板的第一侧上。 第一多个存储器芯片布置在第一芯片层中，第一芯片层覆盖在基板的第二侧。 第一多个存储器芯片的电触点电连接到引脚。 第二多个存储器芯片被布置在第二芯片层中，第二芯片层覆盖第一芯片层。 第二多个存储器芯片的电触点电连接到引脚。
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