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    MEMORY ERASURE INFORMATION IN CACHE LINES
    5.
    发明申请
    MEMORY ERASURE INFORMATION IN CACHE LINES 有权
    缓存行中的内存擦除信息

    公开(公告)号：US20160274968A1

    公开(公告)日：2016-09-22

    申请号：US15034651

    申请日：2013-12-09

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Lidia WARNES ,  Erin A. Handgen ,  Andrew C. Walton

    IPC: G06F11/10 ,  G06F12/12 ,  G06F12/08

    CPC classification number: G06F11/106 ,  G06F11/1016 ,  G06F11/1666 ,  G06F11/20 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/128 ,  G06F2211/1088 ,  G06F2212/1032 ,  G06F2212/466 ,  G06F2212/60 ,  G06F2212/621

    Abstract: Example implementations relate to storing memory erasure information in memory devices on a memory module. In example implementations, a memory location associated with an error in a first cache line may be identified. The first cache line may include data read from the memory location, and the memory location may be in a first memory device of a plurality of memory devices on a memory module. A device number corresponding to the first memory device may be written to one of the plurality of memory devices. When the memory location is read for a second cache line, the device number corresponding to the first memory device may be retrieved. The second cache line may include the retrieved device number and data read from the memory location.

    Abstract translation: 示例性实现涉及将存储器擦除信息存储在存储器模块中的存储器设备中。 在示例实现中，可以识别与第一高速缓存行中的错误相关联的存储器位置。 第一高速缓存行可以包括从存储器位置读取的数据，并且存储器位置可以在存储器模块上的多个存储器设备的第一存储器设备中。 可以将与第一存储器件相对应的器件编号写入多个存储器件中的一个。 当为第二高速缓存行读取存储器位置时，可以检索对应于第一存储器设备的设备号。 第二高速缓存行可以包括检索到的设备号码和从存储器位置读取的数据。

    DRAM ROW SPARING
    6.
    发明申请
    DRAM ROW SPARING 审中-公开

    公开(公告)号：US20170169905A1

    公开(公告)日：2017-06-15

    申请号：US15115971

    申请日：2014-03-03

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Andrew C. Walton ,  Melvin K. Benedict ,  Eric L. Pope ,  Erin A. Handgen

    IPC: G11C29/00 ,  G11C17/16 ,  G06F11/10 ,  G06F3/06

    Abstract: Example implementations relate to dynamic random-access memory (DRAM) row sparing. In example implementations, utilization of a failed row of a DRAM device may be excluded. A fuse in the DRAM device may be blown to replace the failed row with a spare row. The fuse may be blown during runtime operation of the DRAM device. Error-correcting code (ECC) may be used to correct erroneous data from the failed row while the fuse is being blown. Accesses of the failed row may be redirected to the spare row after the fuse is blown.

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