公开(公告)号：US10891185B2

公开(公告)日：2021-01-12

申请号：US15314831

申请日：2014-08-08

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Lidia Warnes ,  Melvin K. Benedict ,  Andrew C. Walton

IPC: G11C29/06 ,  G06F11/10 ,  G11C29/44 ,  G11C29/50 ,  G11C29/12 ,  G06F5/06 ,  G06F11/07 ,  G11C11/41

Abstract: Example implementations relate to tracking memory unit errors on a memory device. In example implementations, a memory device may include on-die error-correcting code (ECC) and a plurality of error counters. One of the plurality of error counters may count errors, detected by the on-die ECC, in a memory unit on the memory device. A post package repair (PPR) may be initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value.

公开(公告)号：US09778982B2

公开(公告)日：2017-10-03

申请号：US15034651

申请日：2013-12-09

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Lidia Warnes ,  Erin A Handgen ,  Andrew C. Walton

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0893 ,  G06F12/128 ,  G06F12/0875 ,  G06F11/20

CPC classification number: G06F11/106 ,  G06F11/1016 ,  G06F11/1666 ,  G06F11/20 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/128 ,  G06F2211/1088 ,  G06F2212/1032 ,  G06F2212/466 ,  G06F2212/60 ,  G06F2212/621

Abstract: Example implementations relate to storing memory erasure information in memory devices on a memory module. In example implementations, a memory location associated with an error in a first cache line may be identified. The first cache line may include data read from the memory location, and the memory location may be in a first memory device of a plurality of memory devices on a memory module. A device number corresponding to the first memory device may be written to one of the plurality of memory devices. When the memory location is read for a second cache line, the device number corresponding to the first memory device may be retrieved. The second cache line may include the retrieved device number and data read from the memory location.

公开(公告)号：US10468118B2

公开(公告)日：2019-11-05

申请号：US15115971

申请日：2014-03-03

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Andrew C. Walton ,  Melvin K. Benedict ,  Eric L. Pope ,  Erin A. Handgen

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/42 ,  G11C29/44 ,  G06F3/06 ,  G11C17/16 ,  G06F12/02 ,  G06F12/06 ,  G11C11/40 ,  G11C29/04

Abstract: Example implementations relate to dynamic random-access memory (DRAM) row sparing. In example implementations, utilization of a failed row of a DRAM device may be excluded. A fuse in the DRAM device may be blown to replace the failed row with a spare row. The fuse may be blown during runtime operation of the DRAM device. Error-correcting code (ECC) may be used to correct erroneous data from the failed row while the fuse is being blown. Accesses of the failed row may be redirected to the spare row after the fuse is blown.

公开(公告)号：US10261852B2

公开(公告)日：2019-04-16

申请号：US14894220

申请日：2013-05-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Melvin K. Benedict ,  Andrew C. Walton

IPC: G06F11/07 ,  G06F11/10 ,  G06F3/06

Abstract: A technique includes accessing error information generated in response to memory errors of a memory device. The error information generated in response to the memory errors of the memory device may then be determined as indicative of a row hammer error for the memory device.

公开(公告)号：US09804972B2

公开(公告)日：2017-10-31

申请号：US14778341

申请日：2013-03-28

Applicant: Hewlett-Packard Enterprise Development LP

Inventor： Melvin K. Benedict ,  William James Walker ,  Andrew C. Walton

IPC: G06F12/123 ,  G06F12/0806 ,  G06F12/0888 ,  G06F12/0891

CPC classification number: G06F12/123 ,  G06F12/0806 ,  G06F12/0888 ,  G06F12/0891 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/22 ,  G06F2212/502 ,  G06F2212/604

Abstract: Activation rates of memory locations associated with memory addresses are monitored. The activation rates of the memory locations associated with the memory addresses are regulated. The regulating of the activation rates of the memory locations associated with the memory addresses includes selectively updating a cache with the memory addresses based on the activation rates.

公开(公告)号：US20170200511A1

公开(公告)日：2017-07-13

申请号：US15313751

申请日：2014-06-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Lidia Warnes ,  Melvin K. Benedict ,  Andrew C. Walton

IPC: G11C29/00 ,  G11C5/14 ,  G11C14/00

CPC classification number: G11C29/70 ,  G11C5/04 ,  G11C5/148 ,  G11C14/0018 ,  G11C29/44 ,  G11C29/808 ,  G11C29/835 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: Example implementations relate to post package repair (PPR) data in non-volatile memory. In example implementations, PPR data may be stored in non-volatile memory on a memory module. PPR data may indicate how many PPRs have been performed on the memory module.

公开(公告)号：US11474706B2

公开(公告)日：2022-10-18

申请号：US14786383

申请日：2013-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Melvin K. Benedict ,  Eric L. Pope ,  Andrew C. Walton

IPC: G06F3/06 ,  G11C11/406 ,  G11C7/02 ,  G11C29/02 ,  G11C11/408 ,  G11C7/10 ,  G11C29/04

Abstract: A technique includes determining, via an analog circuit, where an access rate of a memory row associated with a memory device exceeds a threshold. In various examples, upon a determination that the access rate exceeds the threshold, the technique may further comprise generating an alert to indicate possible corruption of data stored in an adjacent row to the memory row.

公开(公告)号：US20190042341A1

公开(公告)日：2019-02-07

申请号：US16073066

申请日：2016-02-19

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Andrew C. Walton ,  Charles Stuart Johnson ,  Alexander V. Jizrawi

IPC: G06F11/07 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0804 ,  G06F17/50

Abstract: Simulator based detection of a violation of a coherency protocol in an incoherent shared memory system is disclosed. One example is a system including a simulator running on a first computing system, where the simulator simulates a second computing system that is a target for an application to be tested, and where the simulator includes a cache manager to monitor a state of a plurality of simulated caches in an incoherent memory system shared by a plurality of simulated processors, wherein the plurality of simulated processors simulate operations of a respective plurality of processors of the second computing system, and detect a violation of a coherency protocol in the shared memory system, and an alert generator to provide, via a computing device on the first computing system, an alert indicative of the violation.

公开(公告)号：US09935709B2

公开(公告)日：2018-04-03

申请号：US15189525

申请日：2016-06-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Andrew C. Walton ,  Hang Maxime Ung

IPC: H04B10/00 ,  H04B10/114 ,  H04L29/06

CPC classification number: H04B10/1143 ,  H04B10/116 ,  H04L69/22

Abstract: A method, a system, and a non-transitory computer-readable memory resource containing instructions for transmitting data are provided. In an example, the method includes providing a header signal having a first optical property. The header signal indicates a start of a packet, and has a minimum period between transitions that is less than a frame period of a receiving device and greater than a scanline period of the receiving device. A payload signal of the packet is provided that has a second optical property that is different from the first optical property. The payload signal has a minimum period between transitions that is less than the frame period of the receiving device and greater than the scanline period of the receiving device.

公开(公告)号：US20160342341A1

公开(公告)日：2016-11-24

申请号：US15114520

申请日：2014-02-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Douglas L Voigt ,  Andrew C. Walton ,  Boris Zuckerman

IPC: G06F3/06

Abstract: A plurality of mapping modes may be shifted between in real time while maintaining continuous memory mapped access to an application. Data may be migrated between different types storage devices and/or interconnects. The shift between the plurality of mapping modes may be based on a change to the type storage device and/or type of interconnect for the data migration.

Abstract translation: 可以实时地在多个映射模式之间移动，同时保持对应用的连续存储器映射访问。 可以在不同类型的存储设备和/或互连之间迁移数据。 多个映射模式之间的偏移可以基于对类型存储设备的改变和/或用于数据迁移的互连类型。