Image-tone control circuit and gradient adjusting circuit therefor
    1.
    发明授权
    Image-tone control circuit and gradient adjusting circuit therefor 失效
    图像色调控制电路及其梯度调整电路

    公开(公告)号:US5391944A

    公开(公告)日:1995-02-21

    申请号:US986049

    申请日:1992-12-10

    申请人: Hideaki Sadamatsu

    发明人: Hideaki Sadamatsu

    IPC分类号: H04N5/57 H03K5/12

    CPC分类号: H04N5/57

    摘要: In a tone control circuit of luminance signals, an adjusting current is used to add to or subtract from input signals with a gain control. Output signals are thus controlled to have a predetermined gradient based on an arbitrary output setting voltage against the input signals, and an input-output characteristic represented by an arbitrary line graph is obtained by plural gradient adjusting circuits.

    摘要翻译: 在亮度信号的色调控制电路中,调节电流用于通过增益控制来增加或减少输入信号。 因此,输出信号被控制为基于对输入信号的任意输出设定电压具有预定的梯度,并且通过多个梯度调整电路获得由任意线图表示的输入 - 输出特性。

    Video tone correction control circuit
    2.
    发明授权
    Video tone correction control circuit 失效
    视频音调校正控制电路

    公开(公告)号:US5299008A

    公开(公告)日:1994-03-29

    申请号:US835489

    申请日:1992-02-14

    申请人: Hideaki Sadamatsu

    发明人: Hideaki Sadamatsu

    IPC分类号: H04N5/20 H04N5/57

    CPC分类号: H04N5/20

    摘要: A tone correction circuit for a luminance signal which can provide several shapes of correction characteristics. The tone correction circuit comprises a circuit in which the current increases at a first specified voltage or higher and decreases at a second specified voltage or higher so that the current is outputted in a specified range and also provided is a circuit which serves to increase the current at the second specified voltage or higher. Thus, without changing the output voltage at the midpoint, the correction amounts at the minimum point and midpoint, the shifting amount of the midpoint, the correction amounts from to the maximum point and the correction amount at the maximum point, can be controlled so that an optimum output waveform can be obtained in accordance with a scene, and particularly, fuzzy control for the scene can be efficiently made.

    摘要翻译: 一种能够提供多种形状校正特性的亮度信号的色调校正电路。 色调校正电路包括其中电流在第一指定电压或更高处增加并在第二指定电压或更高电压下降低的电路,使得电流在指定范围内输出,并且还提供用于增加电流的电路 在第二规定电压以上。 因此,在不改变中点处的输出电压的情况下,可以控制最小点和中点处的校正量,中点的移动量,从最大点的校正量和最大点的校正量,使得 可以根据场景获得最佳输出波形,特别是可以有效地进行场景的模糊控制。

    Black level compensation circuit for a luminance signal
    3.
    发明授权
    Black level compensation circuit for a luminance signal 失效
    用于亮度信号的黑电平补偿电路

    公开(公告)号:US5262862A

    公开(公告)日:1993-11-16

    申请号:US732000

    申请日:1991-07-18

    CPC分类号: H04N5/20

    摘要: A black compensation circuit for compensating a luminance signal which is subjected to edge enhancement, comprises: a black-level expanding circuit responsive to a control signal including an edge enhancement component and the luminance signal for performing expansion of a tone of a black portion of the luminance signal and for performing conversion of the luminance signal into a black-level expanded signal in the absence of the control signal; a low-pass filter circuit for low-pass filtering the luminance signal to remove the edge enhancement component; a detection circuit responsive to an output of the low-pass filter circuit for detecting the blackest level for a given interval; and a comparing circuit for comparing the blackest level with a given level to produce the control signal, the black-level expanding circuit stopping the expansion and the conversion in the presence of the control signal. The blackest level does not change with sharpness because after the luminance signal subjected to edge enhancement is passed through the low-pass filter, it is sent to the detection circuit. An input signal of the low-pass filter may be supplied from the black-level expanding circuit.

    Semiconductor integrated circuit arrangement for preventing latch up
    4.
    发明授权
    Semiconductor integrated circuit arrangement for preventing latch up 失效
    用于防止放电的半导体集成电路布置

    公开(公告)号:US5237195A

    公开(公告)日:1993-08-17

    申请号:US729584

    申请日:1991-07-15

    申请人: Hideaki Sadamatsu

    发明人: Hideaki Sadamatsu

    CPC分类号: H01L27/0802

    摘要: A semiconductor integrated circuit arrangement prevents the occurrence of latch up. The circuit includes a first semiconductor island of a first conductivity type and a second semiconductor island of the first conductivity type located within a base semiconductor region of a second conductivity type. A resistive diffusion region of the second conductivity type is located within the first semiconductor island region. The second semiconductor region is connected to ground. A high potential electrode connected to the resistive diffusion region is also connected to the first semiconductor island region. In this manner, an emitter and a base of a parasitic transistor of the integrated circuit are connected together to prevent the parasitic transistor from operating in a conductive state, thereby preventing latch up.

    Method of estimating the reliability of module circuits
    5.
    发明授权
    Method of estimating the reliability of module circuits 失效
    估计模块电路可靠性的方法

    公开(公告)号:US5764073A

    公开(公告)日:1998-06-09

    申请号:US651778

    申请日:1996-05-22

    申请人: Hideaki Sadamatsu

    发明人: Hideaki Sadamatsu

    CPC分类号: G01R31/287

    摘要: A method for estimating the reliability of modular circuits by conducting an accelerated life test of components comprising a modular circuit, applying the acceleration factor, etc. on test data thus obtained, and calculating a time to reach a predetermined rate of deterioration as the life time. By adding actual working conditions to the rate of deterioration, a minimum value for determining the deterioration of characteristics is obtained. A component having a value not higher than the minimum value or a rate not lower than the characteristic rate of degradation is then mounted on a printed circuit board comprising the modular circuit, to confirm whether the modular circuit functions normally.

    摘要翻译: 一种用于通过对包含模块化电路的部件进行加速寿命测试,对如此获得的测试数据应用加速因子等来估计模块电路的可靠性的方法,并且计算在寿命期内达到预定的劣化速率的时间 。 通过将实际工作条件与劣化率相加,可以获得确定特性劣化的最小值。 然后将具有不高于最小值的值或不低于特征降解速率的分量安装在包括模块电路的印刷电路板上,以确认模块电路是否正常工作。

    Automatic image-tone control circuit and method for controlling
brightness of image
    6.
    发明授权
    Automatic image-tone control circuit and method for controlling brightness of image 失效
    自动图像色调控制电路及控制图像亮度的方法

    公开(公告)号:US5307166A

    公开(公告)日:1994-04-26

    申请号:US973917

    申请日:1992-11-10

    申请人: Hideaki Sadamatsu

    发明人: Hideaki Sadamatsu

    IPC分类号: H04N5/20 H04N5/14 H04N5/202

    CPC分类号: H04N5/20

    摘要: In a tone control circuit of luminance signals, input-output characteristic having an arbitrary line graph is obtained by plural gradient adjusting circuits in response to frequencies of brightness of the luminance signals which are detected by plural IRE circuits.

    摘要翻译: 在亮度信号的色调控制电路中,响应于由多个IRE电路检测的亮度信号的亮度频率,通过多个梯度调整电路获得具有任意线图的输入 - 输出特性。

    Image signal average picture level detecting apparatus
    7.
    发明授权
    Image signal average picture level detecting apparatus 失效
    图像信号平均图像检测装置

    公开(公告)号:US5223927A

    公开(公告)日:1993-06-29

    申请号:US728245

    申请日:1991-07-10

    IPC分类号: H04N5/14

    CPC分类号: H04N5/14

    摘要: The average picture level (APL) of a video luminance signal is detected, wherein the output of a first current mirror circuit used as the load of a differential amplifying circuit is fed into a smoothing circuit via a second current mirror circuit. The direct current voltage of the output and the detection voltage amplitude may be optionally set without causing an offset voltage in the output average picture level voltage, with the current flowing through the second current mirror circuit being made zero at the time of APL=0%.

    Method for making semiconductor device
    8.
    发明授权
    Method for making semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号:US4536950A

    公开(公告)日:1985-08-27

    申请号:US578036

    申请日:1984-02-08

    摘要: In making a vertical bipolar transistors, after forming by diffusion process a region to become inactive base region an oxide film is selectively formed on the region, thereafter an ion implantation is carried out to produce regions which become the active base region and emitter region by using the oxide film; thereby such a configuration is formed so that defect part (108) induced at the time of the ion implantation is confined in the emitter region, thereby minimizing the leakage current at the PN junction, and hence assuring production of high performance and high reliability semiconductor devices; further, a high integration is attained by adopting self-alignment in forming emitter contact.

    摘要翻译: 在制造垂直双极晶体管时,在通过扩散处理成为非活性基极区域的区域之后,在该区域上选择性地形成氧化物膜,然后进行离子注入以通过使用成为有源基极区域和发射极区域的区域 氧化膜; 从而形成这样的结构,使得在离子注入时引起的缺陷部分(108)被限制在发射极区域中,从而使PN结处的漏电流最小化,从而确保生产高性能和高可靠性的半导体器件 ; 此外,通过在形成发射极接触中采用自对准来实现高集成度。