公开(公告)号：US08546810B2

公开(公告)日：2013-10-01

申请号：US12788343

申请日：2010-05-27

申请人： Hidekazu Miyairi ,  Yasuhiro Jinbo ,  Hiromichi Godo ,  Takafumi Mizoguchi ,  Shinobu Furukawa

发明人： Hidekazu Miyairi ,  Yasuhiro Jinbo ,  Hiromichi Godo ,  Takafumi Mizoguchi ,  Shinobu Furukawa

IPC分类号： H01L27/14 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036

CPC分类号： H01L29/78621 ,  H01L29/04 ,  H01L29/66765

摘要： A thin film transistor in which an effect of photo current is small and an On/Off ratio is high is provided. In a bottom-gate bottom-contact (coplanar) thin film transistor, a channel formation region overlaps with a gate electrode, a first impurity semiconductor layer is provided between the channel formation region and a second impurity semiconductor layer which is in contact with a wiring layer. A semiconductor layer which serves as the channel formation region and the first impurity semiconductor layer preferably overlap with each other in a region where they overlap with the gate electrode. The first impurity semiconductor layer and the second impurity semiconductor layer preferably overlap with each other in a region where they do not overlap with the gate electrode.

摘要翻译： 提供其中光电流的作用小且开/关比高的薄膜晶体管。 在底栅底接触（共面）薄膜晶体管中，沟道形成区域与栅电极重叠，在沟道形成区域和与布线接触的第二杂质半导体层之间设置第一杂质半导体层 层。 用作沟道形成区域和第一杂质半导体层的半导体层优选在与栅电极重叠的区域中彼此重叠。 第一杂质半导体层和第二杂质半导体层优选在不与栅电极重叠的区域中彼此重叠。

公开(公告)号：US08618544B2

公开(公告)日：2013-12-31

申请号：US13167762

申请日：2011-06-24

申请人： Koji Dairiki ,  Takayuki Ikeda ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Daisuke Kawae ,  Takayuki Inoue ,  Satoshi Kobayashi

发明人： Koji Dairiki ,  Takayuki Ikeda ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Daisuke Kawae ,  Takayuki Inoue ,  Satoshi Kobayashi

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/78618 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

摘要翻译： 为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触 同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。

公开(公告)号：US08063403B2

公开(公告)日：2011-11-22

申请号：US13050170

申请日：2011-03-17

申请人： Hiromichi Godo ,  Hidekazu Miyairi

发明人： Hiromichi Godo ,  Hidekazu Miyairi

IPC分类号： H01L29/04

CPC分类号： H01L29/78696 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/66765

摘要： An impurity element imparting one conductivity type is included in a layer close to a gate insulating film of layers with high crystallinity, so that a channel formation region is formed not in a layer with low crystallinity which is formed at the beginning of film formation but in a layer with high crystallinity which is formed later in a microcrystalline semiconductor film. Further, the layer including an impurity element is used as a channel formation region. Furthermore, a layer which does not include an impurity element imparting one conductivity type or a layer which has an impurity element imparting one conductivity type at an extremely lower concentration than other layers, is provided between a pair of semiconductor films including an impurity element functioning as a source region and a drain region and the layer including an impurity element functioning as a channel formation region.

摘要翻译： 赋予一种导电类型的杂质元素被包括在接近具有高结晶度的层的栅极绝缘膜的层中，使得沟道形成区不形成在成膜开始时形成的低结晶度的层中 稍后在微晶半导体膜中形成的具有高结晶度的层。 此外，使用包括杂质元素的层作为沟道形成区域。 此外，在包含杂质元素的一对半导体膜之间设置不含有赋予一种导电型的杂质元素的层或具有赋予比其他层低的浓度的一种导电型的杂质元素的层， 源区和漏区，该层包括用作沟道形成区的杂质元素。

公开(公告)号：US08624321B2

公开(公告)日：2014-01-07

申请号：US12398295

申请日：2009-03-05

申请人： Shunpei Yamazaki ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Hidekazu Miyairi

发明人： Shunpei Yamazaki ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Hidekazu Miyairi

IPC分类号： H01L23/62

CPC分类号： H01L29/78696 ,  H01L29/04 ,  H01L29/66765

摘要： A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided over the amorphous semiconductor layer and to which an impurity element imparting one conductivity type is added to form a source region and a drain region. The gate insulating layer has a step adjacent to a portion in contact with an end portion of the microcrystalline semiconductor layer. A second thickness of the gate insulating layer in a portion outside the microcrystalline semiconductor layer is smaller than a first thickness thereof in a portion in contact with the microcrystalline semiconductor layer.

摘要翻译： 提供一种薄膜晶体管，其包括覆盖栅极的栅极绝缘层，设置在栅极绝缘层上的微晶半导体层，与微晶半导体层和栅极绝缘层重叠的非晶半导体层，以及一对杂质半导体 提供在非晶半导体层上并且添加赋予一种导电类型的杂质元素以形成源区和漏区的层。 栅极绝缘层具有与微晶半导体层的端部接触的部分相邻的台阶。 在与微晶半导体层接触的部分中，微晶半导体层外部的栅极绝缘层的第二厚度小于其第一厚度。

公开(公告)号：US07812348B2

公开(公告)日：2010-10-12

申请号：US12390954

申请日：2009-02-23

申请人： Koji Dairiki ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae ,  Satoshi Kobayashi

发明人： Koji Dairiki ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae ,  Satoshi Kobayashi

IPC分类号： H01L27/14

CPC分类号： H01L29/78609 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78669

摘要： A thin-film transistor in which problems with ON-state current and OFF-state current are solved, and a thin-film transistor capable of high-speed operation. The thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions, provided with a space therebetween so as to be overlapped with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of semiconductor layers in which an impurity element which serves as an acceptor is added, overlapped over the gate insulating layers with the gate electrode and the impurity semiconductor layers, and disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer being in contact with the gate insulating layer and the pair of semiconductor layers and extended between the pair of semiconductor layers.

摘要翻译： 解决了导通状态电流和截止电流的问题的薄膜晶体管，以及能够进行高速运转的薄膜晶体管。 薄膜晶体管包括一对杂质半导体层，其中添加赋予一种导电类型的杂质元素以形成源极和漏极区域，其间具有间隔，以便与具有栅极绝缘层的栅电极重叠 插入在栅电极和杂质半导体层之间; 添加作为受体的杂质元素的一对半导体层，与栅极电极和杂质半导体层重叠在栅极绝缘层上，并且在沟道长度方向上间隔设置; 以及与所述栅绝缘层和所述一对半导体层接触并在所述一对半导体层之间延伸的非晶半导体层。

公开(公告)号：US07968880B2

公开(公告)日：2011-06-28

申请号：US12391398

申请日：2009-02-24

申请人： Koji Dairiki ,  Takayuki Ikeda ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Daisuke Kawae ,  Takayuki Inoue ,  Satoshi Kobayashi

发明人： Koji Dairiki ,  Takayuki Ikeda ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Daisuke Kawae ,  Takayuki Inoue ,  Satoshi Kobayashi

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/78618 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

摘要翻译： 为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触 同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。

公开(公告)号：US08120030B2

公开(公告)日：2012-02-21

申请号：US12633067

申请日：2009-12-08

申请人： Hiromichi Godo ,  Satoshi Kobayashi ,  Hidekazu Miyairi ,  Toshiyuki Isa ,  Shunpei Yamazaki

发明人： Hiromichi Godo ,  Satoshi Kobayashi ,  Hidekazu Miyairi ,  Toshiyuki Isa ,  Shunpei Yamazaki

IPC分类号： H01L29/04

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/04

摘要： Off current of a bottom gate thin film transistor in which a semiconductor layer is shielded from light by a gate electrode is reduced. A thin film transistor includes a gate electrode layer; a first semiconductor layer; a second semiconductor layer, provided on and in contact with the first semiconductor layer; a gate insulating layer between and in contact with the gate electrode layer and the first semiconductor layer; impurity semiconductor layers in contact with the second semiconductor layer; and source and drain electrode layers partially in contact with the impurity semiconductor layers and the first and second semiconductor layers. The entire surface of the first semiconductor layer on the gate electrode layer side is covered by the gate electrode layer; and a potential barrier at a portion where the first semiconductor layer is in contact with the source or drain electrode layer is 0.5 eV or more.

摘要翻译： 其中半导体层被栅极电极遮挡光的底栅薄膜晶体管的截止电流减小。 薄膜晶体管包括栅电极层; 第一半导体层; 第二半导体层，设置在第一半导体层上并与第一半导体层接触; 在栅极电极层和第一半导体层之间并与之接触的栅极绝缘层; 与第二半导体层接触的杂质半导体层; 以及与杂质半导体层和第一和第二半导体层部分接触的源极和漏极电极层。 栅极电极层侧的第一半导体层的整个表面被栅电极层覆盖; 并且在第一半导体层与源极或漏极电极层接触的部分处的势垒为0.5eV以上。

公开(公告)号：US07923730B2

公开(公告)日：2011-04-12

申请号：US12273027

申请日：2008-11-18

申请人： Hiromichi Godo ,  Hidekazu Miyairi

发明人： Hiromichi Godo ,  Hidekazu Miyairi

IPC分类号： H01L29/10

CPC分类号： H01L29/78696 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/66765

摘要： An impurity element imparting one conductivity type is included in a layer close to a gate insulating film of layers with high crystallinity, so that a channel formation region is formed not in a layer with low crystallinity which is formed at the beginning of film formation but in a layer with high crystallinity which is formed later in a microcrystalline semiconductor film. Further, the layer including an impurity element is used as a channel formation region. Furthermore, a layer which does not include an impurity element imparting one conductivity type or a layer which has an impurity element imparting one conductivity type at an extremely lower concentration than other layers, is provided between a pair of semiconductor films including an impurity element functioning as a source region and a drain region and the layer including an impurity element functioning as a channel formation region.

公开(公告)号：US07786485B2

公开(公告)日：2010-08-31

申请号：US12390144

申请日：2009-02-20

申请人： Koji Dairiki ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae ,  Satoshi Kobayashi

发明人： Koji Dairiki ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae ,  Satoshi Kobayashi

IPC分类号： H01L27/14 ,  H01L29/04 ,  H01L29/15

CPC分类号： H01L27/1214 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765

摘要： A thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions so as to be overlapped at least partly with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of conductive layers which is overlapped over the gate insulating layers at least partly with the gate electrode and the impurity semiconductor layers, and is disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer which is in contact with the gate insulating layer and the pair of conductive layers and is extended between the pair of conductive layers.

摘要翻译： 薄膜晶体管包括一对杂质半导体层，其中添加赋予一种导电类型的杂质元素以形成源极区和漏极区，以至少部分地与栅电极重叠，栅极绝缘层介于 栅电极和杂质半导体层; 一对导电层，其至少部分地与所述栅电极和所述杂质半导体层重叠在所述栅极绝缘层上方，并且在沟道长度方向上设置有间隔; 以及与所述栅极绝缘层和所述一对导电层接触并在所述一对导电层之间延伸的非晶半导体层。

公开(公告)号：US08709836B2

公开(公告)日：2014-04-29

申请号：US13175990

申请日：2011-07-05

申请人： Hidekazu Miyairi ,  Takafumi Mizoguchi

发明人： Hidekazu Miyairi ,  Takafumi Mizoguchi

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： An object is to provide a method for manufacturing a thin film transistor and a display device with reduced number of masks, in which adverse effects of optical current are suppressed. A manufacturing method comprises forming a stack including, from bottom to top, a light-blocking film, a base film, a first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film; performing first etching on the whole thickness of the stack using a first resist mask formed over it; forming a gate electrode layer by side etching the first conductive film in a second etching; forming a second resist mask over the stack; and performing third etching down to the semiconductor film, and partially etching it, using the second resist mask to form a source and drain electrode layer, a source and drain region, and a semiconductor layer.

摘要翻译： 本发明的目的是提供一种制造薄膜晶体管的方法和减少数量的掩模的显示装置，其中抑制了光电流的不利影响。 一种制造方法，包括从底部到顶部形成包括遮光膜，基底膜，第一导电膜，第一绝缘膜，半导体膜，杂质半导体膜和第二导电膜的堆叠体; 使用形成在其上的第一抗蚀剂掩模对堆叠的整个厚度执行第一蚀刻; 在第二蚀刻中通过侧蚀刻所述第一导电膜形成栅极电极; 在堆叠上形成第二抗蚀剂掩模; 并且使用第二抗蚀剂掩模对半导体膜执行第三蚀刻并部分蚀刻，以形成源极和漏极电极层，源极和漏极区域以及半导体层。