公开(公告)号：US07397092B2

公开(公告)日：2008-07-08

申请号：US11364950

申请日：2006-03-01

申请人： Hideki Horii ,  Suk-Ho Joo ,  Ji-Hye Yi

发明人： Hideki Horii ,  Suk-Ho Joo ,  Ji-Hye Yi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

摘要翻译： 可相变存储器件可以包括衬底，衬底上的绝缘层，第一和第二电极以及第一和第二电极之间的相变材料的图案。 更具体地，绝缘层可以在其中具有孔，并且第一电极可以在绝缘层中的孔中。 此外，第二电极的部分可以延伸超过相变材料图案的边缘。 还讨论了相关方法。

公开(公告)号：US07037749B2

公开(公告)日：2006-05-02

申请号：US10780246

申请日：2004-02-18

申请人： Hideki Horii ,  Suk-Ho Joo ,  Ji-Hye Yi

发明人： Hideki Horii ,  Suk-Ho Joo ,  Ji-Hye Yi

IPC分类号： H01L21/00 ,  H01L51/40

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

摘要翻译： 可相变存储器件可以包括衬底，衬底上的绝缘层，第一和第二电极以及第一和第二电极之间的相变材料的图案。 更具体地，绝缘层可以在其中具有孔，并且第一电极可以在绝缘层中的孔中。 此外，第二电极的部分可以延伸超过相变材料图案的边缘。 还讨论了相关方法。

公开(公告)号：US07763878B2

公开(公告)日：2010-07-27

申请号：US12132920

申请日：2008-06-04

申请人： Hideki Horii ,  Suk-Ho Joo ,  Ji-Hye Yi

发明人： Hideki Horii ,  Suk-Ho Joo ,  Ji-Hye Yi

IPC分类号： H01L45/00

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

摘要翻译： 可相变存储器件可以包括衬底，衬底上的绝缘层，第一和第二电极以及第一和第二电极之间的相变材料的图案。 更具体地，绝缘层可以在其中具有孔，并且第一电极可以在绝缘层中的孔中。 此外，第二电极的部分可以延伸超过相变材料图案的边缘。 还讨论了相关方法。

公开(公告)号：US20060148125A1

公开(公告)日：2006-07-06

申请号：US11364950

申请日：2006-03-01

申请人： Hideki Horii ,  Suk-ho Joo ,  Ji-Hye Yi

发明人： Hideki Horii ,  Suk-ho Joo ,  Ji-Hye Yi

IPC分类号： H01L21/00

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

摘要翻译： 可相变存储器件可以包括衬底，衬底上的绝缘层，第一和第二电极以及第一和第二电极之间的相变材料的图案。 更具体地，绝缘层可以在其中具有孔，并且第一电极可以在绝缘层中的孔中。 此外，第二电极的部分可以延伸超过相变材料图案的边缘。 还讨论了相关方法。

公开(公告)号：US20080272357A1

公开(公告)日：2008-11-06

申请号：US12132920

申请日：2008-06-04

申请人： Hideki Horii ,  Suk-Ho Joo ,  Ji-Hye Yi

发明人： Hideki Horii ,  Suk-Ho Joo ,  Ji-Hye Yi

IPC分类号： H01L47/00

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

摘要翻译： 可相变存储器件可以包括衬底，衬底上的绝缘层，第一和第二电极以及第一和第二电极之间的相变材料的图案。 更具体地，绝缘层可以在其中具有孔，并且第一电极可以在绝缘层中的孔中。 此外，第二电极的部分可以延伸超过相变材料图案的边缘。 还讨论了相关方法。

公开(公告)号：US07569430B2

公开(公告)日：2009-08-04

申请号：US11674580

申请日：2007-02-13

申请人： Jun-Soo Bae ,  Hideki Horii ,  Ji-Hye Yi ,  Young-Soo Lim

发明人： Jun-Soo Bae ,  Hideki Horii ,  Ji-Hye Yi ,  Young-Soo Lim

IPC分类号： H01L21/82

CPC分类号： H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： The present invention relates to a phase changeable structure having decreased amounts of defects and a method of forming the phase changeable structure. A stacked composite is first formed by (i) forming a phase changeable layer including a chalcogenide is formed on a lower electrode, (ii) forming an etch stop layer having a first etch rate with respect to a first etching material including chlorine on the phase changeable layer, and (iii) forming a conductive layer having a second etch rate with respect to the first etching material on the etch stop layer. The conductive layer of the stacked composite is then etched using the first etching material to form an upper electrode. The etch stop layer and the phase changeable layer are then etched using a second etching material that is substantially flee of chlorine to form an etch stop pattern and a phase changeable pattern, respectively.

摘要翻译： 本发明涉及具有减少的缺陷量的相变结构和形成相变结构的方法。 首先通过（i）在下电极上形成包括硫族化物的相变层来形成堆叠复合体，（ii）形成相对于在相上包括氯的第一蚀刻材料具有第一蚀刻速率的蚀刻停止层 可变层，和（iii）形成相对于蚀刻停止层上的第一蚀刻材料具有第二蚀刻速率的导电层。 然后使用第一蚀刻材料蚀刻层叠复合体的导电层以形成上电极。 然后使用基本上不含氯的第二蚀刻材料来蚀刻蚀刻停止层和相变层，以分别形成蚀刻停止图案和相变图案。

公开(公告)号：US08426916B2

公开(公告)日：2013-04-23

申请号：US13476121

申请日：2012-05-21

申请人： Myung-Sun Kim ,  Hwa-Sung Rhee ,  Ho Lee ,  Ji-Hye Yi

发明人： Myung-Sun Kim ,  Hwa-Sung Rhee ,  Ho Lee ,  Ji-Hye Yi

IPC分类号： H01L21/36

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.

摘要翻译： 提供制造半导体集成电路器件的方法。 基板设置有形成在第一和第二区域上的栅极图案。 第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。 源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。 形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。 第二SiGe外延层直接形成在第一SiGe外延层上，以使用不同于第一硅源气体的第二硅源气体来进一步填充源极/漏极沟槽。

公开(公告)号：US08207033B2

公开(公告)日：2012-06-26

申请号：US12419698

申请日：2009-04-07

申请人： Myung-Sun Kim ,  Hwa-Sung Rhee ,  Ho Lee ,  Ji-Hye Yi

发明人： Myung-Sun Kim ,  Hwa-Sung Rhee ,  Ho Lee ,  Ji-Hye Yi

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.

摘要翻译： 提供制造半导体集成电路器件的方法。 基板设置有形成在第一和第二区域上的栅极图案。 第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。 源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。 形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。 直接在第一SiGe外延层上形成第二SiGe外延层，以使用不同于第一硅源气体的第二硅源气体来进一步填充源/漏沟槽。

公开(公告)号：US06998306B2

公开(公告)日：2006-02-14

申请号：US10747449

申请日：2003-12-30

申请人： Woo-Sik Kim ,  Ji-Hye Yi

发明人： Woo-Sik Kim ,  Ji-Hye Yi

IPC分类号： H01L21/8234

CPC分类号： H01L27/108 ,  Y10S257/903 ,  Y10S257/904

摘要： The present invention discloses a semiconductor memory device having a multiple tunnel junction pattern and a method of forming the same. The semiconductor memory device includes a unit cell composed of planar transistor and vertical transistors. The planar transistor includes first and second conductive regions formed at predetermined regions of a semiconductor substrate and a storage node stacked on a channel region therebetween. The vertical transistor includes a storage node, a multiple tunnel junction pattern stacked thereon, a data line stacked thereon, and a word line for covering both sidewalls of the storage node and the multiple tunnel junction pattern. Width of the multiple tunnel junction pattern is narrower than the storage node and data lines. Semiconductor layers and tunnel oxide layers are alternately and repeatedly stacked and anisotropically etched to form the multiple tunnel junction pattern of narrow width while forming the data line and the storage node.

公开(公告)号：US06635921B2

公开(公告)日：2003-10-21

申请号：US10146897

申请日：2002-05-17

申请人： Ji-Hye Yi ,  Woo-Sik Kim

发明人： Ji-Hye Yi ,  Woo-Sik Kim

IPC分类号： H01L29788

CPC分类号： H01L21/28273 ,  H01L21/32134 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881 ,  H01L29/88

摘要： A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunnel junction layer pattern sequentially stacked on a channel region between the first and second conductive regions, a data line stacked on the multiple tunnel junction layer pattern, and a wordline covering both sidewalls of the storage node and of the multiple tunnel junction layer pattern, wherein both sidewalls of the storage node have undercut regions for increasing the overlapping area of the storage node and a wordline. The storage node is formed by alternately and repeatedly stacking first and second conductive layers having different etch rates, successively patterning the conductive layers to form a storage node pattern, and selectively and isotropically etching the first or second conductive layer of the storage node pattern.