公开(公告)号：US4821299A

公开(公告)日：1989-04-11

申请号：US15347

申请日：1987-02-17

申请人： Hideki Kawai ,  Masaru Fujii ,  Kiyoto Ohta ,  Masahiko Sakagami

发明人： Hideki Kawai ,  Masaru Fujii ,  Kiyoto Ohta ,  Masahiko Sakagami

IPC分类号： G11C19/00 ,  G11C19/18 ,  G11C19/28 ,  H03K23/54

CPC分类号： G11C19/188

摘要： In a semiconductor integrated circuit device having at least one shift register, a plurality of 5 stages of the shift register are electrically connected in series, the 1st stage of said shift register is located in the closest position to the data input terminal, and other succeeding stages are sequentially and straightly located at intervals; the chain of the stages is folded at a particular stage, and further succeeding stages are sequentially and straightly located at intervals so as to fill in the spaces between the other stages, thus, the unbalance of the load capacitance between said stages and the functional unbalance between the shift registers can be minimized.

摘要翻译： 在具有至少一个移位寄存器的半导体集成电路器件中，移位寄存器的多个5级串联电连接，所述移位寄存器的第1级位于与数据输入端最接近的位置， 阶段是以间隔顺序和直线定位的; 阶段的链条在特定阶段被折叠，并且进一步的后续阶段以间隔顺序和直线地定位，以便填充其他阶段之间的空间，因此，所述阶段之间的负载电容的不平衡和功能不平衡 移位寄存器之间可以最小化。

公开(公告)号：US4845670A

公开(公告)日：1989-07-04

申请号：US15348

申请日：1987-02-17

申请人： Toshio Nishimoto ,  Hideki Kawai ,  Masaru Fujii ,  Kiyoto Ohta

发明人： Toshio Nishimoto ,  Hideki Kawai ,  Masaru Fujii ,  Kiyoto Ohta

IPC分类号： G11C19/28 ,  G11C7/10 ,  G11C19/00

CPC分类号： G11C7/1036

摘要： In a memory device, a shift-register comprises a plurality of stages for transferring sequentially a pair of signals which have mutually opposite phases. Each stage has a comparator circuit which compares the pair of signals and generates a pair of fixed voltage signals. By this construction, high-speed operation of the memory device, low power consumptions, and high-capacity load driving are achieved.

摘要翻译： 在存储装置中，移位寄存器包括用于顺序地传送具有相反相位的一对信号的多个级。 每个级具有比较器电路，其比较该对信号并产生一对固定电压信号。 通过这种结构，实现了存储器件的高速运行，低功耗和高容量负载驱动。

公开(公告)号：US4796224A

公开(公告)日：1989-01-03

申请号：US15349

申请日：1987-02-17

申请人： Hideki Kawai ,  Masaru Fujii ,  Kiyoto Ohta ,  Yoshikazu Maeyama

发明人： Hideki Kawai ,  Masaru Fujii ,  Kiyoto Ohta ,  Yoshikazu Maeyama

IPC分类号： G11C7/00 ,  G11C5/02 ,  G11C11/401 ,  G11C11/41

CPC分类号： G11C5/025

摘要： In a semiconductor memory device, a memory cell array is separated into at least two portions on a substrate, and a serial memory element, such as a shift register, and control signal lines are collectively disposed between the two memory cell array portions, and by this arrangement, the length of the control signal lines and data lines can be minimized so that the stray or parasitic capacitance is reduced, and a higher speed and stable operation of the device is thereby realized.

摘要翻译： 在半导体存储装置中，将存储单元阵列分离为基板上的至少两个部分，并且诸如移位寄存器的串行存储元件和控制信号线共同设置在两个存储单元阵列部分之间，并且由 通过这种布置，可以使控制信号线和数据线的长度最小化，从而减小杂散或寄生电容，从而实现装置的更高的速度和稳定的操作。

公开(公告)号：US5065052A

公开(公告)日：1991-11-12

申请号：US538244

申请日：1990-06-14

申请人： Masahiko Sakagami ,  Hideki Kawai

发明人： Masahiko Sakagami ,  Hideki Kawai

IPC分类号： G11C11/407 ,  G06F13/16 ,  G06F13/364 ,  G11C11/401 ,  H03K17/00

CPC分类号： G06F13/364 ,  G06F13/1605

摘要： This invention is realized, in sum, by providing at least one reset input terminal, aside from a reset input terminal to which a request end signal is supplied, to output stage RS flip-flops of plural latch circuits to which plural request signals are supplied respectively. The signal of a first output terminal of the output stage RS flip-flop of a specified latch circuit of the plural latch circuits is supplied to a reset input terminal of the output stage RS flip-flop of the other latch circuit and a delay circuit is connected between a second output terminal and the other reset input terminal of the output stage RS flip-flops of each latch circuit. Accordingly, if plural request signals are supplied at substantially the same time, the competition of these request signals may be settled. Besides, by setting the delay time of each delay circuit longer than the time required from the supply of the signal to the set input terminal of the corresponding output stage RS flip-flop until the signal is latched in the output terminal, even if pulsive signals are supplied to the output stage RS flip-flops, oscillation of the output stage RS flip-flops may be prevented.

公开(公告)号：US06665757B1

公开(公告)日：2003-12-16

申请号：US09545279

申请日：2000-04-07

申请人： Shoichi Tsujita ,  Masaru Fujii ,  Tatsuhiro Hosokawa ,  Tsutomu Sekibe ,  Hiroshi Sakurai ,  Hideki Kawai

发明人： Shoichi Tsujita ,  Masaru Fujii ,  Tatsuhiro Hosokawa ,  Tsutomu Sekibe ,  Hiroshi Sakurai ,  Hideki Kawai

IPC分类号： G06F1342

CPC分类号： G06F13/4081 ,  Y02D10/14 ,  Y02D10/151

摘要： A communication interface of the present invention includes a clock signal line, a first signal line, a second signal line and one or more data signal lines as communication signal lines between a master system and a slave system.

摘要翻译： 本发明的通信接口包括作为主系统和从系统之间的通信信号线的时钟信号线，第一信号线，第二信号线和一个或多个数据信号线。

公开(公告)号：US08676738B2

公开(公告)日：2014-03-18

申请号：US13062174

申请日：2009-08-26

申请人： Hideki Kawai

发明人： Hideki Kawai

IPC分类号： G06F17/00 ,  G06N5/02

CPC分类号： G06F17/30734

摘要： For a group of elements defined with a first relationship between elements stored in a first data memory unit and a second relationship therebetween different from the first relationship stored in a second data memory unit, a relationship detector includes a first distance calculating unit that calculates a predetermined first distance between the two elements belonging to the group in the first relationship, a second distance calculating unit that calculates a predetermined second distance between the two elements belonging to the group in the second relationship, and an unpredictability calculating unit that calculates a dissociation level between the first distance and the second distance between the two elements belonging to the group through a predetermined rule.

摘要翻译： 对于由存储在第一数据存储单元中的元素之间的第一关系定义的元件与不同于存储在第二数据存储单元中的第一关系的第二关系定义的一组元件，关系检测器包括：第一距离计算单元， 属于第一关系中的组的两个元素之间的第一距离，第二距离计算单元，其计算属于该第二关系中的该组的两个元素之间的预定第二距离;以及不可预测性计算单元， 通过预定规则，属于该组的两个元件之间的第一距离和第二距离。

公开(公告)号：US08653304B2

公开(公告)日：2014-02-18

申请号：US13497819

申请日：2010-09-30

申请人： Hiroaki Kaneko ,  Hideki Kawai ,  Yosuke Iura ,  Hideki Inoue ,  Mie Kaino ,  Hiroyuki Meguro ,  Tazuru Uchida

发明人： Hiroaki Kaneko ,  Hideki Kawai ,  Yosuke Iura ,  Hideki Inoue ,  Mie Kaino ,  Hiroyuki Meguro ,  Tazuru Uchida

IPC分类号： C07C275/26 ,  C07C275/28 ,  A61K31/17

CPC分类号： C07D309/06 ,  C07C275/34 ,  C07C275/40 ,  C07C275/42 ,  C07C2601/04 ,  C07C2602/08 ,  C07D295/135

摘要： A 2,3-dihydro-1H-indene-2-yl urea represented by Formula (Ia) or a pharmaceutically acceptable salt thereof:

摘要翻译： 由式（Ia）表示的2,3-二氢-1H-茚-2-基脲或其药学上可接受的盐：

公开(公告)号：US08545807B2

公开(公告)日：2013-10-01

申请号：US12920244

申请日：2009-02-26

申请人： Yasuchika Hasegawa ,  Hideki Kawai ,  Tsuyoshi Kawai

发明人： Yasuchika Hasegawa ,  Hideki Kawai ,  Tsuyoshi Kawai

IPC分类号： A61K51/00 ,  A61M36/14

CPC分类号： C07F9/5345 ,  C07F5/003 ,  C09D11/037 ,  C09D11/50 ,  C09K11/06 ,  C09K2211/182

摘要： The present invention has been created to provide a near infrared high emission rare-earth complex having an excellent light-emitting property in the near infrared region. The near infrared high emission rare-earth complex of the present invention is characterized in that its structure is expressed by the following general formula (1): where Ln(III) represents a trivalent rare-earth ion; n is an integer equal to or greater than three; Xs represent either the same member or different members selected from a hydrogen atom, a deuterium atom, halogen atoms, C1-C20 groups, hydroxyl groups, nitro groups, amino groups, sulfonyl groups, cyano groups, silyl groups, phosphonic groups, diazo groups and mercapto groups; and Z represents a bidentate ligand.

摘要翻译： 本发明的目的是提供一种在近红外区域具有优异的发光特性的近红外高发射稀土配合物。 本发明的近红外高发射稀土配合物的特征在于其结构由以下通式（1）表示：其中Ln（III）表示三价稀土离子; n是等于或大于3的整数; Xs表示选自氢原子，氘原子，卤原子，C1-C20基，羟基，硝基，氨基，磺酰基，氰基，甲硅烷基，膦酸基，重氮基的相同成员或不同成员 和巯基; Z表示双齿配体。

公开(公告)号：US20130080215A1

公开(公告)日：2013-03-28

申请号：US13702098

申请日：2011-06-06

申请人： Hideki Kawai

发明人： Hideki Kawai

IPC分类号： G06Q10/06

CPC分类号： G06Q10/06395

摘要： Activity information obtainer (10a) of intellectual productivity measurement device (100) obtains activity information representing an activity. Event information obtainer (10b) obtains information representing an event and including a time at which the event occurs. Evaluation obtainer (4) obtains a subjective evaluation. Short-term-context input section (11a) generates a short-term context from the activity information. Long-term-context input section (11b) extracts a long-term context from event information. Model generator (5) generates, using a mapping function from a direct sum space of the space of the short-term context and the space of the long-term context to the space of the subjective evaluation, an estimation model that is a parameter of the mapping function in such a way that values reflecting the short-term context and the long-term context enter within the range of the subjective evaluation. Intellectual productivity calculator (6) calculates an intellectual productivity using the estimation model.

摘要翻译： 智力生产力测量装置（100）的活动信息获取器（10a）获得表示活动的活动信息。 事件信息获取器（10b）获取表示事件并包括事件发生的时间的信息。 评估者（4）获得主观评价。 短期上下文输入部分（11a）从活动信息生成短期上下文。 长期上下文输入部分（11b）从事件信息中提取长期上下文。 模型生成器（5）使用从短期上下文的空间的直接和空间和长期上下文的空间到主观评估空间的映射函数生成估计模型，该估计模型是 映射函数以反映短期语境和长期语境的值进入主观评价范围内。 智力生产率计算器（6）使用估计模型计算智力生产力。

公开(公告)号：US20130056240A1

公开(公告)日：2013-03-07

申请号：US13697551

申请日：2010-10-29

申请人： Hideki Kawai

发明人： Hideki Kawai

IPC分类号： H01B3/48

CPC分类号： H02G3/0481 ,  H02G3/0468

摘要： Disclosed is a wire protection member that covers and protects a wire. The wire protection member includes a main body portion that is formed by application of heat and pressure to a nonwoven material so as to cover an outer circumferential portion of a wire bundle and a plurality of protruding portions that is formed by application of heat and pressure to a nonwoven material so as to project outward from an outer circumferential portion of the main body portion.

摘要翻译： 公开了一种覆盖并保护电线的电线保护元件。 线保护构件包括主体部分，其通过对非织造材料施加热和压力而形成，以覆盖线束的外周部分和通过施加热和压力而形成的多个突出部分 非织造材料，以便从主体部分的外周部向外突出。