公开(公告)号：US5065052A

公开(公告)日：1991-11-12

申请号：US538244

申请日：1990-06-14

申请人： Masahiko Sakagami ,  Hideki Kawai

发明人： Masahiko Sakagami ,  Hideki Kawai

IPC分类号： G11C11/407 ,  G06F13/16 ,  G06F13/364 ,  G11C11/401 ,  H03K17/00

CPC分类号： G06F13/364 ,  G06F13/1605

摘要： This invention is realized, in sum, by providing at least one reset input terminal, aside from a reset input terminal to which a request end signal is supplied, to output stage RS flip-flops of plural latch circuits to which plural request signals are supplied respectively. The signal of a first output terminal of the output stage RS flip-flop of a specified latch circuit of the plural latch circuits is supplied to a reset input terminal of the output stage RS flip-flop of the other latch circuit and a delay circuit is connected between a second output terminal and the other reset input terminal of the output stage RS flip-flops of each latch circuit. Accordingly, if plural request signals are supplied at substantially the same time, the competition of these request signals may be settled. Besides, by setting the delay time of each delay circuit longer than the time required from the supply of the signal to the set input terminal of the corresponding output stage RS flip-flop until the signal is latched in the output terminal, even if pulsive signals are supplied to the output stage RS flip-flops, oscillation of the output stage RS flip-flops may be prevented.

公开(公告)号：US4821299A

公开(公告)日：1989-04-11

申请号：US15347

申请日：1987-02-17

申请人： Hideki Kawai ,  Masaru Fujii ,  Kiyoto Ohta ,  Masahiko Sakagami

发明人： Hideki Kawai ,  Masaru Fujii ,  Kiyoto Ohta ,  Masahiko Sakagami

IPC分类号： G11C19/00 ,  G11C19/18 ,  G11C19/28 ,  H03K23/54

CPC分类号： G11C19/188

摘要： In a semiconductor integrated circuit device having at least one shift register, a plurality of 5 stages of the shift register are electrically connected in series, the 1st stage of said shift register is located in the closest position to the data input terminal, and other succeeding stages are sequentially and straightly located at intervals; the chain of the stages is folded at a particular stage, and further succeeding stages are sequentially and straightly located at intervals so as to fill in the spaces between the other stages, thus, the unbalance of the load capacitance between said stages and the functional unbalance between the shift registers can be minimized.

摘要翻译： 在具有至少一个移位寄存器的半导体集成电路器件中，移位寄存器的多个5级串联电连接，所述移位寄存器的第1级位于与数据输入端最接近的位置， 阶段是以间隔顺序和直线定位的; 阶段的链条在特定阶段被折叠，并且进一步的后续阶段以间隔顺序和直线地定位，以便填充其他阶段之间的空间，因此，所述阶段之间的负载电容的不平衡和功能不平衡 移位寄存器之间可以最小化。

公开(公告)号：US07307866B2

公开(公告)日：2007-12-11

申请号：US11132196

申请日：2005-05-19

申请人： Kunisato Yamaoka ,  Hiroshige Hirano ,  Yasushi Gohou ,  Shunichi Iwanari ,  Yasuo Murakuki ,  Masahiko Sakagami ,  Tetsuji Nakakuma ,  Takashi Miki

发明人： Kunisato Yamaoka ,  Hiroshige Hirano ,  Yasushi Gohou ,  Shunichi Iwanari ,  Yasuo Murakuki ,  Masahiko Sakagami ,  Tetsuji Nakakuma ,  Takashi Miki

IPC分类号： G11C11/22 ,  G11C11/42 ,  G11C5/14 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C11/22

摘要： A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.

摘要翻译： 本发明的铁电存储器包括：多个正常单元，每个单元包括用于保持数据的第一铁电电容器和连接到第一铁电电容器的第一电极的第一晶体管; 连接到第一晶体管的第一位线; 第一位线预充电电路，其是设置在第一位线和地之间的开关电路; 以及连接到第一晶体管的栅极的字线。 在驱动第一位线预充电电路以放电第一位线的电位之前，字线被去激活以将第一铁电电容器与第一位线断开。

公开(公告)号：US07280406B2

公开(公告)日：2007-10-09

申请号：US11344199

申请日：2006-02-01

申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

IPC分类号： G11C16/06

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2207/229

摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

摘要翻译： 提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。 同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

公开(公告)号：US20050146969A1

公开(公告)日：2005-07-07

申请号：US11023663

申请日：2004-12-29

申请人： Yasuo Murakuki ,  Masahiko Sakagami ,  Shunichi Iwanari

发明人： Yasuo Murakuki ,  Masahiko Sakagami ,  Shunichi Iwanari

IPC分类号： G01R31/28 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C17/18 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C17/18 ,  G11C29/785

摘要： A semiconductor memory apparatus is provided which has a simple circuit configuration and is capable of randomly accessing fuse data. In the semiconductor memory apparatus of the present invention, a fuse cell 30 including a fuse 31 is connected to a pair of bit lines of a memory circuit. The fuse 31 and a fuse data output circuit (which includes a resistor 32 and an inverter 33) are connected to a pair of bit lines BLT and BLB of the memory circuit through a fuse selection switch 34. In the semiconductor memory apparatus of the present invention, by allowing a column decoder 12 for selecting a pair of bit lines of the memory cell to also function as a decoder circuit for selecting a fuse, the bit lines of the memory circuit can be used as signal lines for outputting fuse data, whereby the circuit size is reduced and the circuit area is reduced.

摘要翻译： 提供一种半导体存储装置，其具有简单的电路配置并且能够随机访问熔丝数据。 在本发明的半导体存储装置中，包括熔丝31的熔丝单元30连接到存储电路的一对位线。 熔丝31和熔丝数据输出电路（其包括电阻32和反相器33）通过熔丝选择开关34连接到存储电路的一对位线BLT和BLB。 在本发明的半导体存储装置中，通过允许用于选择存储单元的一对位线的列解码器12也用作用于选择熔丝的解码器电路，存储电路的位线可以用作 用于输出熔丝数据的信号线，由此减小电路尺寸并减小电路面积。

公开(公告)号：US20050265090A1

公开(公告)日：2005-12-01

申请号：US11121939

申请日：2005-05-05

申请人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

发明人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C29/00 ,  G11C29/12

CPC分类号： G11C29/816 ,  G11C11/22 ,  G11C29/789 ,  G11C2029/4402

摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

摘要翻译： 为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。 半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。 选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

公开(公告)号：US06320229B1

公开(公告)日：2001-11-20

申请号：US09301354

申请日：1999-04-29

申请人： Toshitaka Uchikoba ,  Masahiko Sakagami ,  Akihiro Yamamoto

发明人： Toshitaka Uchikoba ,  Masahiko Sakagami ,  Akihiro Yamamoto

IPC分类号： H01L2974

CPC分类号： H01L27/0288 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In a semiconductor substrate of a first conductivity type, first and second high-concentration layers of a second conductivity type are formed in spaced relation to each other. A reference voltage is applied to the second high-concentration layer. A conductive layer provides an electrical connection between the first high-concentration layer and an input pad for inputting an input signal to an input circuit or input/output circuit. A first low-concentration layer of the second conductivity type is formed in the region of the semiconductor substrate immediately underlying the first high-concentration layer.

摘要翻译： 在第一导电类型的半导体衬底中，第二导电类型的第一和第二高浓度层彼此间隔开地形成。 对第二高浓度层施加参考电压。 导电层在第一高浓度层和输入焊盘之间提供电连接，用于将输入信号输入到输入电路或输入/输出电路。 在第一高浓度层正下方的半导体衬底的区域中形成第二导电类型的第一低浓度层。

公开(公告)号：US5233557A

公开(公告)日：1993-08-03

申请号：US723613

申请日：1991-07-01

申请人： Masahiko Sakagami ,  Yoshikazu Maeyama

发明人： Masahiko Sakagami ,  Yoshikazu Maeyama

IPC分类号： G11C11/413 ,  G06F1/06 ,  G11C7/22

CPC分类号： G11C7/22

摘要： A memory control device for controlling a random access memory provides with an arbiter for generating write start and read start signals in response to WRITE and READ commands which are obtained by frequency-dividing writing and reading clock signals, respectively and a memory control circuit comprised of first and second delay circuits for delaying the write start and read start signals by predetermined times, respectively, and first and second RS flip-flop circuits for generating write and read control signals in response to the write start and read start signals, respectively, which are reset by reset signals output from the first and second delay circuits, respectively.

公开(公告)号：US5227697A

公开(公告)日：1993-07-13

申请号：US618800

申请日：1990-11-28

申请人： Masahiko Sakagami

发明人： Masahiko Sakagami

IPC分类号： G11C7/20 ,  G11C11/4072

CPC分类号： G11C7/20 ,  G11C11/4072

摘要： A dynamic type semiconductor memory in which a bit line is made to be connected to an electric potential different from a precharge potential after a precharge of the bit line is effected and one of word lines is selected and before a sensing amplifier operates. Thereby, all data stored in memory cells of the same row address can be cleared or preset in a cycle. Further, data stored in all of memory cells of which the number is equal to that of row addresses multiplied by that of column addresses can be cleared or preset in cycles of which the number is equal to that of the row addresses. Consequently, a clearance of contents of or a presetting of all memory cells can be effected at a high speed.

公开(公告)号：US07468900B2

公开(公告)日：2008-12-23

申请号：US11356213

申请日：2006-02-17

申请人： Kunisato Yamaoka ,  Hiroshige Hirano ,  Masahiko Sakagami

发明人： Kunisato Yamaoka ,  Hiroshige Hirano ,  Masahiko Sakagami

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： In order to omit a reset transistor between a storage node and a cell plate line of a memory cell, a cell plate line is fixed to a potential substantially equal to a ground potential and a bit line is driven with positive and negative voltages.

摘要翻译： 为了省略存储单元的存储节点和单元板极线之间的复位晶体管，单元板线固定为基本上等于接地电位的电位，并且用正和负电压驱动位线。