公开(公告)号：US6060747A

公开(公告)日：2000-05-09

申请号：US159122

申请日：1998-09-23

申请人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba ,  Noboru Matsuda ,  Masanobu Tsuchitani

发明人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba ,  Noboru Matsuda ,  Masanobu Tsuchitani

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/739

CPC分类号： H01L29/0696

摘要： A semiconductor device is characterized in that source electrode contact regions, each of which is formed of a first conductivity type source layer and a second conductivity type base layer in a surface of a semiconductor surface, are formed at respective intersectional points of a diagonally-arranged lattice, and in that a trench having a gate electrode buried therein is formed so as to snake through the contact regions alternately. By virtue of the structure, the trench arrangement and source/base simultaneous contact quality are improved, to thereby increase a trench density (channel density) per unit area.

摘要翻译： 半导体器件的特征在于，在对角线布置的各个交点处形成源极电极接触区域，每个源极电极接触区域由半导体表面的第一导电型源极层和第二导电型基极层形成， 并且具有埋入其中的具有栅电极的沟槽形成为交替地穿过接触区域。 通过该结构，提高了沟槽布置和源极/基极同时接触质量，从而增加了每单位面积的沟槽密度（沟道密度）。

公开(公告)号：US20060145290A1

公开(公告)日：2006-07-06

申请号：US11294411

申请日：2005-12-06

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

IPC分类号： H01L29/00 ,  H01L21/425 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7802

摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

公开(公告)号：US06995426B2

公开(公告)日：2006-02-07

申请号：US10327937

申请日：2002-12-26

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7802

摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

摘要翻译： 半导体器件包括形成在第一导电类型的半导体层中的扩散区域。 扩散区域分别包括第一和第二导电类型的第一和第二杂质扩散区域。 扩散区域具有由第一和第二杂质扩散区域的杂质浓度限定的第一和第二区域。 第一和第二区域之间的结点形成在第一和第二杂质扩散区域彼此重叠的部分中。 在第一或第二区域的半导体层的平面方向上的杂质浓度的周期小于半导体层的平面方向上的构成第一或第二区域的第一和第二杂质扩散区域的最大宽度 第二区。

公开(公告)号：US6010950A

公开(公告)日：2000-01-04

申请号：US026508

申请日：1998-02-19

申请人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba

发明人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba

IPC分类号： H01L21/02 ,  H01L21/18 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/30

CPC分类号： H01L21/18 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76251 ,  H01L21/76264

摘要： The most distinctive feature of the present invention lies in that a warp and crystal defects can be prevented from occurring and a processing margin for forming an isolation groove can be improved in an intelligent power device including a power element section and an IC control section within one chip. A bonded wafer is obtained by bonding an active-layer substrate and a supporting substrate with an epitaxially grown silicon layer interposed therebetween so as to cover an oxide film selectively formed at the interface of the active-layer substrate. Isolation trenches are then formed in the bonded wafer to such a depth as to reach the oxide film from the element forming surface of the active-layer substrate. Thus, an IC controller is formed within a dielectric isolation region surrounded with the isolation trenches and the oxide film and accordingly the IC controller can effectively be isolated by a dielectric.

摘要翻译： 本发明的最显着的特征在于，可以防止发生翘曲和晶体缺陷，并且可以在包括功率元件部分和IC控制部分的智能功率器件的一个智能功率器件内改善用于形成隔离沟槽的加工余量 芯片。 通过将有源层衬底和支撑衬底与外延生长的硅层接合以便覆盖在有源层衬底的界面处有选择地形成的氧化物膜而获得接合晶片。 然后在接合的晶片中形成隔离沟槽到从活性层衬底的元件形成表面到达氧化物膜的深度。 因此，在由隔离沟槽和氧化物膜包围的电介质隔离区域内形成IC控制器，因此可以通过电介质来有效地隔离IC控制器。

公开(公告)号：US07262477B2

公开(公告)日：2007-08-28

申请号：US10694903

申请日：2003-10-29

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiro Osawa ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiro Osawa ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa

IPC分类号： H01L21/8238 ,  H01L29/00

CPC分类号： H01L21/76224 ,  H01L21/316 ,  H01L21/31695 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/7802

摘要： There is provided a semiconductor device including a semiconductor substrate with a trench, and a particulate insulating layer filling at least a lower portion of the trench and containing insulating particles. The semiconductor device may further include a reflowable dielectric layer covering an upper surface of the particulate insulating layer, the insulating particles being stable at the melting point or the softening point of the reflowable dielectric layer.

摘要翻译： 提供了一种包括具有沟槽的半导体衬底和填充至少沟槽的下部并且包含绝缘颗粒的颗粒绝缘层的半导体器件。 半导体器件还可以包括覆盖颗粒绝缘层的上表面的可回流电介质层，绝缘颗粒在可回流电介质层的熔点或软化点是稳定的。

公开(公告)号：US07423315B2

公开(公告)日：2008-09-09

申请号：US11265208

申请日：2005-11-03

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa ,  Satoshi Taji ,  Kenichi Tokano

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa ,  Satoshi Taji ,  Kenichi Tokano

IPC分类号： H01L29/36

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/7811

摘要： The present application provides a semiconductor device including a first-conductivity type semiconductor substrate, a pillar structure portion formed on the first-conductivity type semiconductor substrate and formed of five semiconductor pillar layers arranged in one direction parallel to a main surface of the first-conductivity type semiconductor substrate, and isolation insulating portions formed on the first-conductivity type semiconductor substrate and sandwiching the pillar structure portion between the isolation insulating portions, wherein the pillar structure portion is formed of a first first-conductivity type pillar layer, a second first-conductivity type pillar layer and a third first-conductivity type pillar layer which sandwich the first first-conductivity type pillar layer, a first second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the second first-conductivity type pillar layer, and a second second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the third first-conductivity type pillar layer.

摘要翻译： 本申请提供了一种半导体器件，其包括第一导电型半导体衬底，形成在第一导电型半导体衬底上的柱结构部分，并且由平行于第一导电型主要表面的一个方向排列的五个半导体柱层 以及形成在第一导电型半导体基板上并将柱结构部分夹在隔离绝缘部分之间的隔离绝缘部分，其中柱结构部分由第一第一导电型柱层，第二第一导电型支柱层， 导电型柱层和夹着第一第一导电型柱层的第三第一导电型柱层，设置在第一第一导电型柱层和第二第一导电型柱之间的第一第二导电型柱层 层和第二第二导电类型 柱层，设置在第一第一导电型柱层和第三第一导电型柱层之间。

公开(公告)号：US20060043480A1

公开(公告)日：2006-03-02

申请号：US10991433

申请日：2004-11-19

申请人： Masanobu Tsuchitani ,  Tetsuo Matsuda ,  Hideki Okumura ,  Atsuko Yamashita

发明人： Masanobu Tsuchitani ,  Tetsuo Matsuda ,  Hideki Okumura ,  Atsuko Yamashita

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/66712 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/42368 ,  H01L29/7811

摘要： A semiconductor device comprises a semiconductor layer which includes a terminate end part and a cell formation part that is surrounded by this end part, and a plurality of guard rings each of which is formed at the end part to surround the cell formation part. These guard rings are made shallower and smaller in width as they get near to the guard ring that resides at the outside position.

摘要翻译： 半导体器件包括半导体层，其包括终端部分和由该端部部分包围的电池形成部分，以及多个保护环，每个保护环形成在端部处以围绕电池形成部分。 这些保护环的宽度越来越小，因为它们靠近位于外部位置的防护环。

公开(公告)号：US20060108600A1

公开(公告)日：2006-05-25

申请号：US11265208

申请日：2005-11-03

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa ,  Satoshi Taji ,  Kenichi Tokano

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa ,  Satoshi Taji ,  Kenichi Tokano

IPC分类号： H01L29/423

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/7811

摘要： The present application provides a semiconductor device including a first-conductivity type semiconductor substrate, a pillar structure portion formed on the first-conductivity type semiconductor substrate and formed of five semiconductor pillar layers arranged in one direction parallel to a main surface of the first-conductivity type semiconductor substrate, and isolation insulating portions formed on the first-conductivity type semiconductor substrate and sandwiching the pillar structure portion between the isolation insulating portions, wherein the pillar structure portion is formed of a first first-conductivity type pillar layer, a second first-conductivity type pillar layer and a third first-conductivity type pillar layer which sandwich the first first-conductivity type pillar layer, a first second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the second first-conductivity type pillar layer, and a second second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the third first-conductivity type pillar layer.

摘要翻译： 本申请提供了一种半导体器件，其包括第一导电型半导体衬底，形成在第一导电型半导体衬底上的柱结构部分，并且由平行于第一导电型主要表面的一个方向排列的五个半导体柱层 以及形成在第一导电型半导体基板上并将柱结构部分夹在隔离绝缘部分之间的隔离绝缘部分，其中柱结构部分由第一第一导电型柱层，第二第一导电型支柱层， 导电型柱层和夹着第一第一导电型柱层的第三第一导电型柱层，设置在第一第一导电型柱层和第二第一导电型柱之间的第一第二导电型柱层 层和第二第二导电类型 柱层，设置在第一第一导电型柱层和第三第一导电型柱层之间。

公开(公告)号：US07420245B2

公开(公告)日：2008-09-02

申请号：US11194609

申请日：2005-08-02

申请人： Atsuko Yamashita ,  Tetsuo Matsuda ,  Hideki Okumura ,  Masanobu Tsuchitani

发明人： Atsuko Yamashita ,  Tetsuo Matsuda ,  Hideki Okumura ,  Masanobu Tsuchitani

IPC分类号： H01L29/94

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

摘要： A first semiconductor pillar layer of a first conductivity type is formed on a main surface of a semiconductor substrate of the first conductivity type. A second semiconductor pillar layer of a second conductivity type is formed adjacent to the first semiconductor pillar layer. A third semiconductor pillar layer of the first conductivity type is formed adjacent to the second semiconductor pillar layer. A semiconductor base layer of the second conductivity type is formed on the main surface of the second semiconductor pillar layer. An insulated-gate type semiconductor element is formed in the semiconductor base layer. The carrier concentration on the side of a main surface of each of said first through third semiconductor pillar layers is higher than a carrier concentration on the opposite side of said main surface in each of said first through third semiconductor pillar layers.

摘要翻译： 第一导电类型的第一半导体柱层形成在第一导电类型的半导体衬底的主表面上。 形成与第一半导体柱层相邻的第二导电类型的第二半导体柱层。 形成与第二半导体柱层相邻的第一导电类型的第三半导体柱层。 第二导电类型的半导体基底层形成在第二半导体柱层的主表面上。 在半导体基底层中形成绝缘栅型半导体元件。 所述第一〜第三半导体柱层的主表面侧的载流子浓度高于所述第一〜第三半导体柱层的所述主面的相对侧的载流子浓度。

公开(公告)号：US20060043481A1

公开(公告)日：2006-03-02

申请号：US11194609

申请日：2005-08-02

申请人： Atsuko Yamashita ,  Tetsuo Matsuda ,  Hideki Okumura ,  Masanobu Tsuchitani

发明人： Atsuko Yamashita ,  Tetsuo Matsuda ,  Hideki Okumura ,  Masanobu Tsuchitani

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

摘要： A first semiconductor pillar layer of a first conductivity type is formed on a main surface of a semiconductor substrate of the first conductivity type. A second semiconductor pillar layer of a second conductivity type is formed adjacent to the first semiconductor pillar layer. A third semiconductor pillar layer of the first conductivity type is formed adjacent to the second semiconductor pillar layer. A semiconductor base layer of the second conductivity type is formed on the main surface of the second semiconductor pillar layer. An insulated-gate type semiconductor element is formed in the semiconductor base layer. The carrier concentration on the side of a main surface of each of said first through third semiconductor pillar layers is higher than a carrier concentration on the opposite side of said main surface in each of said first through third semiconductor pillar layers.

摘要翻译： 第一导电类型的第一半导体柱层形成在第一导电类型的半导体衬底的主表面上。 形成与第一半导体柱层相邻的第二导电类型的第二半导体柱层。 形成与第二半导体柱层相邻的第一导电类型的第三半导体柱层。 第二导电类型的半导体基底层形成在第二半导体柱层的主表面上。 在半导体基底层中形成绝缘栅型半导体元件。 所述第一〜第三半导体柱层的主表面侧的载流子浓度高于所述第一〜第三半导体柱层的所述主面的相对侧的载流子浓度。