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    Semiconductor memory device and semiconductor memory system
    1.
    发明授权
    Semiconductor memory device and semiconductor memory system 有权
    半导体存储器件和半导体存储器系统

    公开(公告)号：US07876626B2

    公开(公告)日：2011-01-25

    申请号：US12408232

    申请日：2009-03-20

    申请人： Hideo Mukai ,  Hiroshi Maejima ,  Satoru Takase ,  Naoya Tokiwa ,  Katsuaki Isobe

    发明人： Hideo Mukai ,  Hiroshi Maejima ,  Satoru Takase ,  Naoya Tokiwa ,  Katsuaki Isobe

    IPC分类号： G11C7/00

    CPC分类号： G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2207/2263 ,  G11C2211/5647 ,  G11C2213/31 ,  G11C2213/56 ,  G11C2213/72

    摘要： A semiconductor memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operative to compare certain length data read out by the read/write circuit from plural ones of the memory cells with certain length data to be written in the plural memory cells to make a decision, and create a flag representing the decision result. The read/write circuit inverts each bit in the certain length data to be written in the memory cells in accordance with the flag, and writes only rewrite-intended data of the certain length data and the flag. The read/write circuit reads the certain length data together with the flag corresponding thereto, and inverts each bit in the certain length data in accordance with the flag.

    摘要翻译： 半导体存储器件包括存储单元阵列，其包括布置在字线和位线的交点处的多个存储单元; 读/写电路，用于执行对存储器单元的数据读/写; 以及操作电路，用于将来自多个存储器单元的读/写电路读出的某些长度数据与要写入多个存储器单元的一定长度数据进行比较，并作出决定，并创建表示决定结果的标志 。 读/写电路根据该标志反转要写入存储单元的一定长度数据中的每个位，并且仅写入特定长度数据和标志的重写预期数据。 读/写电路读取与其对应的标志一定的长度数据，并根据该标志反转一定长度数据中的每一位。

    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM 有权
    半导体存储器件和半导体存储器系统

    公开(公告)号：US20090237979A1

    公开(公告)日：2009-09-24

    申请号：US12408232

    申请日：2009-03-20

    申请人： Hideo Mukai ,  Hiroshi Maejima ,  Satoru Takase ,  Naoya Tokiwa ,  Katsuaki Isobe

    发明人： Hideo Mukai ,  Hiroshi Maejima ,  Satoru Takase ,  Naoya Tokiwa ,  Katsuaki Isobe

    IPC分类号： G11C11/00 ,  G11C7/22

    CPC分类号： G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2207/2263 ,  G11C2211/5647 ,  G11C2213/31 ,  G11C2213/56 ,  G11C2213/72

    摘要： A semiconduct or memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operative to compare certain length data read out by the read/write circuit from plural ones of the memory cells with certain length data to be written in the plural memory cells to make a decision, and create a flag representing the decision result. The read/write circuit inverts each bit in the certain length data to be written in the memory cells in accordance with the flag, and writes only rewrite-intended data of the certain length data and the flag. The read/write circuit reads the certain length data together with the flag corresponding thereto, and inverts each bit in the certain length data in accordance with the flag.

    摘要翻译： 半导体或存储器件包括存储单元阵列，其包括布置在字线和位线的交点处的多个存储单元; 读/写电路，用于执行对存储器单元的数据读/写; 以及操作电路，用于将来自多个存储器单元的读/写电路读出的某些长度数据与要写入多个存储器单元的一定长度数据进行比较，并作出决定，并创建表示决定结果的标志 。 读/写电路根据该标志反转要写入存储单元的一定长度数据中的每个位，并且仅写入特定长度数据和标志的重写预期数据。 读/写电路读取与其对应的标志一定的长度数据，并根据该标志反转一定长度数据中的每一位。

    NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME
    4.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 审中-公开
    非易失性存储器件及其控制方法

    公开(公告)号：US20090219750A1

    公开(公告)日：2009-09-03

    申请号：US12394487

    申请日：2009-02-27

    申请人： Naoya TOKIWA ,  Hiroshi Maejima ,  Hideo Mukai

    发明人： Naoya TOKIWA ,  Hiroshi Maejima ,  Hideo Mukai

    IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C17/12 ,  G11C5/02 ,  G11C8/08 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

    摘要： A nonvolatile memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistive element; a line selector circuit operative to decode an address signal to select the first and second lines; and a control circuit operative to execute control on at least one of data erase, write and read for the memory cell connected between the first and second lines selected at the line selector circuit. The control circuit executes control based on one parameter selected among a plurality of parameters. The line selector circuit specifies the parameter based on a first address portion in the address signal and selects the first and second lines based on a second address portion in the address signal.

    摘要翻译： 非易失性存储器件包括存储单元阵列，其包括第一和第二相交线以及布置在第一和第二线的交点处的电可擦除可编程存储单元，每个存储单元包含可变电阻元件; 行选择器电路，用于解码地址信号以选择第一和第二行; 以及控制电路，用于对连接在线选择器电路中选择的第一和第二线之间的存储单元的数据擦除，写入和读取中的至少一个执行控制。 控制电路基于从多个参数中选择的一个参数来执行控制。 线选择器电路基于地址信号中的第一地址部分来指定参数，并且基于地址信号中的第二地址部分选择第一和第二行。

    Nonvolatile semiconductor memory device
    5.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08427885B2

    公开(公告)日：2013-04-23

    申请号：US13315967

    申请日：2011-12-09

    申请人： Hideo Mukai ,  Hiroshi Maejima ,  Katsuaki Isobe

    发明人： Hideo Mukai ,  Hiroshi Maejima ,  Katsuaki Isobe

    IPC分类号： G11C7/10

    CPC分类号： G11C8/14 ,  G11C7/18 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/72

    摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.

    摘要翻译： 一种非易失性半导体存储器件，包括具有以矩阵形式设置的多个MAT（单位阵列）的单元阵列，所述MAT各包括多条第一线，与第一线交叉的多条第二线，以及 存储单元连接在第一和第二线之间。 该装置还包括第一和第二驱动电路，选择连接到每个MAT的存储器单元的第一和第二线，所述存储器单元被访问，并且驱动所选择的第一和第二行来写入或读取数据。 存储单元通过连接到从MAT中选择的每个第一行形成页面。 该设备还包括以页为单位锁存写入或读取数据的数据锁存器，其中第一和第二驱动电路多次驱动第一和第二行以写入或读取单元阵列中的一页的数据。

    NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND DATA WRITING METHOD THEREFOR
    6.
    发明申请
    NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND DATA WRITING METHOD THEREFOR 有权
    非易失性半导体存储器件及其数据写入方法

    公开(公告)号：US20120201070A1

    公开(公告)日：2012-08-09

    申请号：US13415953

    申请日：2012-03-09

    申请人： Hiroshi Maejima ,  Katsuaki Isobe ,  Hideo Mukai

    发明人： Hiroshi Maejima ,  Katsuaki Isobe ,  Hideo Mukai

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C7/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

    摘要： A nonvolatile semiconductor storage device includes first and second intersecting wires; a electrically rewritable memory cell disposed at each intersection of the first second wires, including a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires. The control circuit precharges a non-selected second wire to a standby voltage larger than a reference voltage prior to programming a variable resistor connected to selected first and second wires by supplying the reference voltage to a non-selected first wire and the selected second wire, applying to the selected first wire a program voltage for programming of the selected variable resistor and applying to the non-selected second wire a control voltage which prevents the rectifying device from turning ON.

    摘要翻译： 非易失性半导体存储装置包括第一和第二相交线; 在第一第二导线的交点设置有包含用于将电阻值作为数据非易失性地存储的可变电阻器和整流装置的电可重写存储单元串联连接; 以及控制电路，其向第一和第二导线施加写入数据所需的电压。 在通过将参考电压提供给未选择的第一线和所选择的第二线之前，控制电路将未选择的第二线预充电至大于参考电压的待机电压，然后再对连接到所选择的第一和第二线的可变电阻进行编程， 向所选择的第一线施加用于对所选择的可变电阻器进行编程的编程电压，并向未选择的第二线施加防止整流装置导通的控制电压。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20100097832A1

    公开(公告)日：2010-04-22

    申请号：US12580795

    申请日：2009-10-16

    申请人： Hideo MUKAI ,  Hiroshi Maejima ,  Katsuaki Isobe

    发明人： Hideo MUKAI ,  Hiroshi Maejima ,  Katsuaki Isobe

    IPC分类号： G11C11/00 ,  G11C5/02 ,  G11C5/06

    CPC分类号： G11C8/14 ,  G11C7/18 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/72

    摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.

    摘要翻译： 一种非易失性半导体存储器件，包括具有以矩阵形式设置的多个MAT（单位阵列）的单元阵列，所述MAT各包括多条第一线，与第一线交叉的多条第二线，以及 存储单元连接在第一和第二线之间。 该装置还包括第一和第二驱动电路，选择连接到每个MAT的存储器单元的第一和第二线，所述存储器单元被访问，并且驱动所选择的第一和第二行来写入或读取数据。 存储单元通过连接到从MAT中选择的每个第一行形成页面。 该设备还包括以页为单位锁存写入或读取数据的数据锁存器，其中第一和第二驱动电路多次驱动第一和第二行以写入或读取单元阵列中的一页的数据。

    Nonvolatile semiconductor memory device
    8.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08089818B2

    公开(公告)日：2012-01-03

    申请号：US12580795

    申请日：2009-10-16

    申请人： Hideo Mukai ,  Hiroshi Maejima ,  Katsuaki Isobe

    发明人： Hideo Mukai ,  Hiroshi Maejima ,  Katsuaki Isobe

    IPC分类号： G11C7/10

    CPC分类号： G11C8/14 ,  G11C7/18 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/72

    摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.

    摘要翻译： 一种非易失性半导体存储器件，包括具有以矩阵形式设置的多个MAT（单位阵列）的单元阵列，所述MAT各包括多条第一线，与第一线交叉的多条第二线，以及 存储单元连接在第一和第二线之间。 该装置还包括第一和第二驱动电路，选择连接到每个MAT的存储器单元的第一和第二线，所述存储器单元被访问，并且驱动所选择的第一和第二行来写入或读取数据。 存储单元通过连接到从MAT中选择的每个第一行形成页面。 该设备还包括以页为单位锁存写入或读取数据的数据锁存器，其中第一和第二驱动电路多次驱动第一和第二行以写入或读取单元阵列中的一页的数据。

    Nonvolatile semiconductor memory device
    9.
    发明授权
    Nonvolatile semiconductor memory device 有权

    公开(公告)号：US08315110B2

    公开(公告)日：2012-11-20

    申请号：US13315967

    申请日：2011-12-09

    申请人： Hideo Mukai ,  Hiroshi Maejima ,  Katsuaki Isobe

    发明人： Hideo Mukai ,  Hiroshi Maejima ,  Katsuaki Isobe

    IPC分类号： G11C7/10

    摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.

    Nonvolatile semiconductor storage device and data writing method therefor
    10.
    发明授权
    Nonvolatile semiconductor storage device and data writing method therefor 有权
    非易失性半导体存储器件及其数据写入方法

    公开(公告)号：US08379432B2

    公开(公告)日：2013-02-19

    申请号：US13415953

    申请日：2012-03-09

    申请人： Hiroshi Maejima ,  Katsuaki Isobe ,  Hideo Mukai

    发明人： Hiroshi Maejima ,  Katsuaki Isobe ,  Hideo Mukai

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C7/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

    摘要： A nonvolatile semiconductor storage device includes first and second intersecting wires; a electrically rewritable memory cell disposed at each intersection of the first second wires, including a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires. The control circuit precharges a non-selected second wire to a standby voltage larger than a reference voltage prior to programming a variable resistor connected to selected first and second wires by supplying the reference voltage to a non-selected first wire and the selected second wire, applying to the selected first wire a program voltage for programming of the selected variable resistor and applying to the non-selected second wire a control voltage which prevents the rectifying device from turning ON.

    摘要翻译： 非易失性半导体存储装置包括第一和第二相交线; 在第一第二配线的交点处配置的电可重写存储单元串联连接，包括用于以非易失性方式存储电阻值作为数据的可变电阻器和整流装置; 以及控制电路，其向第一和第二导线施加写入数据所需的电压。 在通过将参考电压提供给未选择的第一线和所选择的第二线之前，控制电路将未选择的第二线预充电至大于参考电压的待机电压，然后再对连接到所选择的第一和第二线的可变电阻进行编程， 向所选择的第一线施加用于对所选择的可变电阻器进行编程的编程电压，并向未选择的第二线施加防止整流装置导通的控制电压。