摘要:
What is disclosed is an apparatus comprising a transfer gate formed on a substrate and a photodiode formed in the substrate next to the transfer gate. The photodiode comprises a shallow N-type collector formed in the substrate, a deep N-type collector formed in the substrate, wherein a lateral side of the deep N-type collector extends at least under the transfer gate, and a connecting N-type collector formed in the substrate between the deep N-type collector and the shallow N-type collector, wherein the connecting implant connects the deep N-type collector and the shallow N-type collector. Also disclosed is a process comprising forming a deep N-type collector in the substrate, forming a shallow N-type collector formed in the substrate, and forming a connecting N-type collector in the substrate between the deep N-type collector and the shallow N-type collector, wherein the connecting implant connects the deep N-type collector and the shallow N-type collector. A transfer gate is formed on the substrate next to the deep photodiode, wherein a lateral side of the deep N-type collector extends at least under the transfer gate. Other embodiments are disclosed and claimed.
摘要:
The present disclosure introduces a simple method for reducing the capacitance of the floating diffusion node of a CMOS image sensor and consequently improving the image sensor's sensitivity. While reducing parasitic capacitances such as the capacitance between the transfer gate and the floating node, the proposed device layouts, in which the channel width of the detection section is different from the channel width of the photoelectric conversion element, demand no more than what is required for the fabrication of the traditional layouts.
摘要:
A method of operation of a backside illuminated (BSI) pixel array includes acquiring an image signal with a first photosensitive region of a first pixel within the BSI pixel array. The image signal is generated in response to light incident upon a backside of the first pixel. The image signal acquired by the first photosensitive region is transferred to pixel circuitry of the first pixel disposed on a frontside of the first pixel opposite the backside. The pixel circuitry at least partially overlaps the first photosensitive region of the first pixel and extends over die real estate above a second photosensitive region of a second pixel adjacent to the first pixel such that the second pixel donates die real estate unused by the second pixel to the first pixel to accommodate larger pixel circuitry than would fit within the first pixel.
摘要:
A method of operation of a backside illuminated (BSI) pixel array includes acquiring an image signal with a first photosensitive region of a first pixel within the BSI pixel array. The image signal is generated in response to light incident upon a backside of the first pixel. The image signal acquired by the first photosensitive region is transferred to pixel circuitry of the first pixel disposed on a frontside of the first pixel opposite the backside. The pixel circuitry at least partially overlaps the first photosensitive region of the first pixel and extends over die real estate above a second photosensitive region of a second pixel adjacent to the first pixel such that the second pixel donates die real estate unused by the second pixel to the first pixel to accommodate larger pixel circuitry than would fit within the first pixel.
摘要:
A backside illuminated (“BSI”) imaging sensor pixel includes a photodiode region and pixel circuitry. The photodiode region is disposed within a semiconductor die for accumulating an image charge in response to light incident upon a backside of the BSI imaging sensor pixel. The pixel circuitry includes transistor pixel circuitry disposed within the semiconductor die between a frontside of the semiconductor die and the photodiode region. At least a portion of the pixel circuitry overlaps the photodiode region.
摘要:
An image sensor has at least two photodiodes in each unit pixel. A high dynamic range is achieved by selecting different exposure times for the photodiodes. Additionally, blooming is reduced. The readout timing cycle is chosen so that the short exposure time photodiodes act as drains for excess charge overflowing from the long exposure time photodiodes. To improve draining of excess charge, the arrangement of photodiodes may be further selected so that long exposure time photodiodes are neighbored along vertical and horizontal directions by short exposure time photodiodes. A micro-lens array may also be provided in which light is preferentially coupled to the long exposure time photodiodes to improve sensitivity.
摘要:
An image sensor that has a pixel array using an isolation structure between pixels that reduce electrical cross-talk is disclosed. The pixel array is formed on a substrate that has a thin (less than 5 microns) epitaxial layer. The isolation structure uses a deep p-well to surround a shallow trench isolation. The deep p-well is formed using an implant energy of typically over 700 keV.
摘要:
A pixel sensor cell used in a CMOS image sensor is disclosed. The cell includes a pinned photodiode formed in a Pwell that is formed in an N-type semiconductor substrate. A transfer transistor is placed between the pinned photodiode and an output node. A reset transistor is coupled between a high voltage rail Vdd and the output node. Finally, an output transistor with its gate coupled to the output node is provided.
摘要:
An active pixel that incorporates elements of CCD technology into a CMOS image sensor is disclosed. Each pixel includes a reset transistor that resets a sense node. The active pixel includes an amplification transistor that is modulated by the signal on the sense node. A light sensing element, such as a photodiode, is provided and its signal is selectively read out by a transfer gate, selectively stored by a memory gate, and finally read out onto the sense node by a control gate. Underneath the memory gate is a memory well that acts as memory for the pixel and stores the signal output by the light sensing element.
摘要:
A active pixel sensor cell is disclosed that comprises a pinned photodiode. A transfer transistor is placed between the pinned photodiode and an output node, the transfer transistor being a depletion mode N-type MOSFET. A reset transistor is coupled between a high voltage rail Vdd and the output node. Finally, an output transistor has its gate coupled to the output node.