公开(公告)号：US4143388A

公开(公告)日：1979-03-06

申请号：US797835

申请日：1977-05-17

申请人： Hideya Esaki ,  Takashi Hirao ,  Hakuhei Kawakami

发明人： Hideya Esaki ,  Takashi Hirao ,  Hakuhei Kawakami

IPC分类号： H01L29/73 ,  H01L21/266 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L21/266 ,  H01L29/1045 ,  H01L29/42376 ,  H01L29/78

摘要： A MOS type semiconductor device, wherein at least one oblique face is provided on at least a part of a gate electrode which is provided on a principal face of said substrate with a gate insulation film inbetween, and at a specific depth from the oblique face, that is, in parallel with this oblique face, an ion-implanted layer is provided in a manner to obliquely cross the surface of said substrate. In this MOS type semiconductor device the channel is made immediately underneath the surface of the substrate and in the ion-implanted layer, and therefore the channel length is determined by the thickness of the ion-implanted layer. By controlling the thickness of the ion-implanted layer, a short channel length, which is required for improving the operating speed and/or the handling current capability of MOS type semiconductor devices, is obtainable.

公开(公告)号：US5318917A

公开(公告)日：1994-06-07

申请号：US15191

申请日：1993-02-10

申请人： Akihiro Kanda ,  Yoshiro Fujita ,  Takehiro Hirai ,  Mitsuo Tanaka ,  Hideya Esaki

发明人： Akihiro Kanda ,  Yoshiro Fujita ,  Takehiro Hirai ,  Mitsuo Tanaka ,  Hideya Esaki

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L21/28525 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66272 ,  H01L29/7325 ,  Y10S148/011 ,  Y10S148/124

摘要： A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating films extending on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion layer of the first conduction type, a collector contact diffusion layer of the first conduction type; and a base contact diffusion layer of the second conduction type; locating an end of the emitter diffusion layer and a first end of the base contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the emitter lead-out electrode; and locating a second end of the base contact diffusion layer and an end of the collector contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the collector lead-out electrode.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在第一导电类型的半导体衬底中的预定区域中形成基极扩散层，所述基极扩散层为第二导电型; 形成第一绝缘膜，同时在发射极接触形成区域和集电极接触形成区域之上的区域形成发射极引出电极和集电极引出电极，第一绝缘膜在发射极和集电极引线 所述发射极和集电极引出电极包括对应于所述第一导电类型的杂质; 在发射极和集电极引出电极的侧面形成第二绝缘膜; 形成基部接触; 形成包括对应于第二导电类型的杂质的基极引出电极; 扩散来自发射极引出电极，集电极引出电极和基极引出电极的杂质，以形成第一导电类型的发射极扩散层，第一导电类型的集电极接触扩散层; 和第二导电类型的基极接触扩散层; 将发射极扩散层的端部和基极接触扩散层的第一端定位在在发射极引出电极侧延伸的第二绝缘膜的正下方的位置; 以及将所述基极接触扩散层的第二端和所述集电极接触扩散层的端部定位在在所述集电体引出电极的一侧延伸的所述第二绝缘膜的正下方的位置。

公开(公告)号：US06512282B2

公开(公告)日：2003-01-28

申请号：US09778099

申请日：2001-02-07

申请人： Hideya Esaki

发明人： Hideya Esaki

IPC分类号： H01L2900

CPC分类号： H01L29/6659 ,  H01L21/28123 ,  H01L21/823481 ,  H01L29/66545

摘要： A sidewall insulating film is formed on the side faces of a buried gate electrode on a substrate. A trench isolation film, self-aligned with the gate electrode, is also formed so that the upper surface of the isolation film is higher than that of the gate electrode. And source/drain contacts, which make electrical contact with source/drain regions, are formed between the sidewall insulating film and isolation film. Since the source/drain contacts and isolation film are both self-aligned with the gate electrode, no mask overlay margin is needed. Thus, the size of the entire active region and that of the source/drain contacts or source/drain regions can be reduced in the gate length direction.

摘要翻译： 在基板上的掩埋栅电极的侧面上形成侧壁绝缘膜。 还形成了与栅电极自对准的沟槽隔离膜，使得隔离膜的上表面高于栅电极的上表面。 并且在侧壁绝缘膜和隔离膜之间形成与源极/漏极区域电接触的源极/漏极接触点。 由于源极/漏极接触和隔离膜都与栅电极自对准，因此不需要掩模覆盖边缘。 因此，可以在栅极长度方向上减小整个有源区和源极/漏极接触或源极/漏极区的尺寸。

公开(公告)号：US4700329A

公开(公告)日：1987-10-13

申请号：US729347

申请日：1987-10-13

申请人： Toshio Yamada ,  Hideya Esaki

发明人： Toshio Yamada ,  Hideya Esaki

IPC分类号： G11C11/401 ,  G11C11/4099 ,  G11C7/02 ,  G11C7/00

CPC分类号： G11C11/4099

摘要： A semiconductive memory in accordance with the present invention enables the correct setting of the reference electrical potential of a DRAM which is not affected by manufacturing processes by the use of a construction such that, into two dummy cell capacitors having the same capacitance as that of memory cell capacitors for holding information, signals of "1" and "0" or "0" and "1" are respectively written from the first and the second bit lines; thereafter, two dummy cell capacitors are electrically decoupled from the two bit lines and, then, by coupling two dummy cell capacitors, reference charges are obtained, which are then read out.

摘要翻译： 根据本发明的半导体存储器能够通过使用以下结构使得不受制造工艺影响的DRAM的参考电位的正确设置，使得与具有与存储器相同的电容的两个虚拟电池电容器 用于保持信息的单元电容器分别从第一位线和第二位线写入信号“1”和“0”或“0”和“1” 此后，两个虚拟单元电容器与两个位线电耦合，然后通过耦合两个虚拟单元电容器，获得参考电荷，然后读出它们。

公开(公告)号：US06534840B2

公开(公告)日：2003-03-18

申请号：US09774638

申请日：2001-02-01

申请人： Hideya Esaki

发明人： Hideya Esaki

IPC分类号： H01L2900

CPC分类号： H01L29/6659 ,  H01L21/28123 ,  H01L21/823481 ,  H01L29/41775

摘要： A sidewall insulating film is formed on the side faces of a gate electrode on a substrate. A trench isolation film is also formed to be self-aligned with the gate electrode. The upper surface of the trench isolation film reaches a level higher than that of the gate electrode. And source/drain contacts, which make electrical contact with source/drain regions, are formed between the sidewall insulating film and the isolation film. Since the source/drain contacts and the isolation film are both self-aligned with the gate electrode, no mask overlay margin is needed. Thus, the size of the entire active region or the source/drain contacts (or source/drain regions) can be reduced in the gate length direction.

摘要翻译： 在基板上的栅电极的侧面上形成侧壁绝缘膜。 沟槽隔离膜也形成为与栅电极自对准。 沟槽隔离膜的上表面比栅电极的上表面高。 并且在侧壁绝缘膜和隔离膜之间形成与源极/漏极区域电接触的源极/漏极接触点。 由于源极/漏极接触和隔离膜都与栅电极自对准，因此不需要掩模覆盖边缘。 因此，可以在栅极长度方向上减小整个有源区或源极/漏极接触（或源极/漏极区）的尺寸。

公开(公告)号：US5204274A

公开(公告)日：1993-04-20

申请号：US750856

申请日：1991-08-29

申请人： Akihiro Kanda ,  Yoshiro Fujita ,  Takehiro Hirai ,  Mitsuo Tanaka ,  Hideya Esaki

发明人： Akihiro Kanda ,  Yoshiro Fujita ,  Takehiro Hirai ,  Mitsuo Tanaka ,  Hideya Esaki

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/7325 ,  Y10S148/009

摘要： A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating extending films on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion layer of the first conduction type, a collector contact diffusion layer of the first conduction type, and a base contact diffusion layer of the second conduction type; locating an end of the emitter diffusion layer and a first end of the base contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the emitter lead-out electrode; and locating a second end of the base contact diffusion layer and an end of the collector contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the collector lead-out electrode.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在第一导电类型的半导体衬底中的预定区域中形成基极扩散层，所述基极扩散层是第二导电类型; 在发射极接触形成区域和集电极接触形成区域以上的区域中形成第一绝缘膜并同时形成发射极引出电极和集电极引出电极，发射极和集电极引线上的第一绝缘延伸膜 所述发射极和集电极引出电极包括对应于所述第一导电类型的杂质; 在发射极和集电极引出电极的侧面形成第二绝缘膜; 形成基部接触; 形成包括对应于第二导电类型的杂质的基极引出电极; 扩散来自发射极引出电极，集电极引出电极和基极引出电极的杂质，以形成第一导电类型的发射极扩散层，第一导电类型的集电极接触扩散层和 第二导电类型的基极接触扩散层; 将发射极扩散层的端部和基极接触扩散层的第一端定位在在发射极引出电极侧延伸的第二绝缘膜的正下方的位置; 以及将所述基极接触扩散层的第二端和所述集电极接触扩散层的端部定位在在所述集电体引出电极的一侧延伸的所述第二绝缘膜的正下方的位置。

公开(公告)号：US5006717A

公开(公告)日：1991-04-09

申请号：US456994

申请日：1989-12-26

申请人： Noriko Tsutsu ,  Yoshiro Nakata ,  Hideya Esaki

发明人： Noriko Tsutsu ,  Yoshiro Nakata ,  Hideya Esaki

IPC分类号： G01N21/66 ,  G01R31/265

CPC分类号： G01N21/66 ,  G01R31/2656 ,  G01N2021/6421 ,  G01N21/6458

摘要： A method and apparatus for evaluating the lifetime of a semiconductor device are disclosed. Luminescence of a predetermined wavelength which is emitted from an operating semiconductor device is detected. The luminescence of the predetermined wavelength is one which correlates with the degradation of the semiconductor device. Then, the image of detected luminescence of the predetermined wavelength is processed to determine the place of the degradation caused by hot carriers.

摘要翻译： 公开了一种用于评估半导体器件寿命的方法和装置。 检测从操作半导体器件发出的预定波长的发光。 预定波长的发光是与半导体器件的劣化相关的发光。 然后，对预定波长的检测到的发光的图像进行处理，以确定由热载体引起的劣化的位置。