公开(公告)号：US5318917A

公开(公告)日：1994-06-07

申请号：US15191

申请日：1993-02-10

申请人： Akihiro Kanda ,  Yoshiro Fujita ,  Takehiro Hirai ,  Mitsuo Tanaka ,  Hideya Esaki

发明人： Akihiro Kanda ,  Yoshiro Fujita ,  Takehiro Hirai ,  Mitsuo Tanaka ,  Hideya Esaki

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L21/28525 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66272 ,  H01L29/7325 ,  Y10S148/011 ,  Y10S148/124

摘要： A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating films extending on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion layer of the first conduction type, a collector contact diffusion layer of the first conduction type; and a base contact diffusion layer of the second conduction type; locating an end of the emitter diffusion layer and a first end of the base contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the emitter lead-out electrode; and locating a second end of the base contact diffusion layer and an end of the collector contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the collector lead-out electrode.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在第一导电类型的半导体衬底中的预定区域中形成基极扩散层，所述基极扩散层为第二导电型; 形成第一绝缘膜，同时在发射极接触形成区域和集电极接触形成区域之上的区域形成发射极引出电极和集电极引出电极，第一绝缘膜在发射极和集电极引线 所述发射极和集电极引出电极包括对应于所述第一导电类型的杂质; 在发射极和集电极引出电极的侧面形成第二绝缘膜; 形成基部接触; 形成包括对应于第二导电类型的杂质的基极引出电极; 扩散来自发射极引出电极，集电极引出电极和基极引出电极的杂质，以形成第一导电类型的发射极扩散层，第一导电类型的集电极接触扩散层; 和第二导电类型的基极接触扩散层; 将发射极扩散层的端部和基极接触扩散层的第一端定位在在发射极引出电极侧延伸的第二绝缘膜的正下方的位置; 以及将所述基极接触扩散层的第二端和所述集电极接触扩散层的端部定位在在所述集电体引出电极的一侧延伸的所述第二绝缘膜的正下方的位置。

公开(公告)号：US5204274A

公开(公告)日：1993-04-20

申请号：US750856

申请日：1991-08-29

申请人： Akihiro Kanda ,  Yoshiro Fujita ,  Takehiro Hirai ,  Mitsuo Tanaka ,  Hideya Esaki

发明人： Akihiro Kanda ,  Yoshiro Fujita ,  Takehiro Hirai ,  Mitsuo Tanaka ,  Hideya Esaki

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/7325 ,  Y10S148/009

摘要： A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating extending films on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion layer of the first conduction type, a collector contact diffusion layer of the first conduction type, and a base contact diffusion layer of the second conduction type; locating an end of the emitter diffusion layer and a first end of the base contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the emitter lead-out electrode; and locating a second end of the base contact diffusion layer and an end of the collector contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the collector lead-out electrode.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在第一导电类型的半导体衬底中的预定区域中形成基极扩散层，所述基极扩散层是第二导电类型; 在发射极接触形成区域和集电极接触形成区域以上的区域中形成第一绝缘膜并同时形成发射极引出电极和集电极引出电极，发射极和集电极引线上的第一绝缘延伸膜 所述发射极和集电极引出电极包括对应于所述第一导电类型的杂质; 在发射极和集电极引出电极的侧面形成第二绝缘膜; 形成基部接触; 形成包括对应于第二导电类型的杂质的基极引出电极; 扩散来自发射极引出电极，集电极引出电极和基极引出电极的杂质，以形成第一导电类型的发射极扩散层，第一导电类型的集电极接触扩散层和 第二导电类型的基极接触扩散层; 将发射极扩散层的端部和基极接触扩散层的第一端定位在在发射极引出电极侧延伸的第二绝缘膜的正下方的位置; 以及将所述基极接触扩散层的第二端和所述集电极接触扩散层的端部定位在在所述集电体引出电极的一侧延伸的所述第二绝缘膜的正下方的位置。

公开(公告)号：US5331198A

公开(公告)日：1994-07-19

申请号：US924986

申请日：1992-08-05

申请人： Akihiro Kanda ,  Mitsuo Tanaka ,  Takehiro Hirai ,  Masahiro Nakatani

发明人： Akihiro Kanda ,  Mitsuo Tanaka ,  Takehiro Hirai ,  Masahiro Nakatani

IPC分类号： H01L21/74 ,  H01L21/8226 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/730 ,  H01L29/120 ,  H01L29/460

CPC分类号： H01L21/82285 ,  H01L21/743 ,  H01L21/8226 ,  H01L27/0826 ,  Y10S148/087

摘要： The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1) . The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31). The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.

摘要翻译： 本发明提供一种半导体器件，特别是包括集成在同一导电型半导体衬底（1）上的垂直npn晶体管，垂直pnp晶体管和IIL的半导体器件。 IIL包括发射极，基极和集电极，它们分别由高密度n +型第一掩埋层（5），具有比n +型杂质密度低的杂质密度的p +型第二掩埋层（8） 第一掩埋层（5）和n +型扩散层（31）中的至少一个。 这样构成的半导体装置能够提高发射极注入效率，同时保持基极杂质浓度高，并且还可以降低基极宽度，从而可以进一步提高IIL的集电极 - 发射极击穿电压和电流增益， 也可以使IIL的运行速度更高。

公开(公告)号：US5838048A

公开(公告)日：1998-11-17

申请号：US915327

申请日：1997-08-20

申请人： Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

发明人： Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L29/51 ,  H01L27/02 ,  H01L29/68

CPC分类号： H01L29/513 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/518 ,  Y10S148/009

摘要： A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.

摘要翻译： 在硅衬底上形成氧化硅膜和多晶硅膜，并且被选择性地蚀刻以在要形成发射极的区域中形成接触孔。 将多晶硅膜放置在衬底上，并且将两个多晶硅膜图案化以形成由掺杂有砷的两个多晶硅膜制成的发射极电极和栅极电极。 砷从发射电极的多晶硅膜扩散到硅衬底中以形成具有高浓度且浅的N +发射极层。 因此，可以防止栅极绝缘膜的污染，并且可以形成具有高性能的双极晶体管，例如高电流放大因子等。

公开(公告)号：US5406106A

公开(公告)日：1995-04-11

申请号：US76838

申请日：1993-06-15

申请人： Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

发明人： Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L29/51 ,  H01L27/02 ,  H01L27/04 ,  H01L29/68

CPC分类号： H01L29/513 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/518

摘要： A silicon oxide film as a dielectric film and a silicon nitride film or a polysilicon film as a protection film for the silicon oxide film are formed on a silicon substrate. After the two films are selectively etched to form contact holes of a bipolar transistor, a polysilicon film as a conductive film is laid on the entire substrate and selectively etched to form electrodes. In a MIS transistor, the protection film of the silicon nitride film serves as a gate insulator film and the protection film of the polysilicon film serves as a gate electrode. Accordingly, contamination to the gate insulator film at formation of contact holes of the bipolar transistor is prevented, and an excellent semiconductor with Bi-MOS structure is manufactured with low cost.

摘要翻译： 在硅衬底上形成作为电介质膜的氧化硅膜和作为氧化硅膜保护膜的氮化硅膜或多晶硅膜。 在选择性地蚀刻两个膜以形成双极晶体管的接触孔之后，将作为导电膜的多晶硅膜铺设在整个基板上并选择性地蚀刻以形成电极。 在MIS晶体管中，氮化硅膜的保护膜用作栅极绝缘膜，多晶硅膜的保护膜用作栅电极。 因此，防止了在形成双极晶体管的接触孔时对栅极绝缘膜的污染，并以低成本制造了具有Bi-MOS结构的优良半导体。

公开(公告)号：US5323054A

公开(公告)日：1994-06-21

申请号：US907470

申请日：1992-07-01

申请人： Akihiro Kanda ,  Mitsuo Tanaka ,  Takehiro Hirai ,  Masahiro Nakatani

发明人： Akihiro Kanda ,  Mitsuo Tanaka ,  Takehiro Hirai ,  Masahiro Nakatani

IPC分类号： H01L21/74 ,  H01L21/8226 ,  H01L27/082 ,  H01L29/165 ,  H01L29/700

CPC分类号： H01L21/8226 ,  H01L21/743 ,  H01L27/0826

摘要： In a a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same substrate, grooves that reach an n.sup.+ -type buried layer 5 serving as an emitter of the IIL and an n.sup.+ -type buried layer 4 serving as a collector of the vertical npn transistor are formed at the same time, and an oxide film 101 is formed only on the sidewall of each groove; in the grooves, n.sup.+ -type polycrystalline silicon films 103 and 102 are formed, which are made to serve as an emitter lead-out portion of the IIL and a collector wall of the vertical npn transistor, respectively; a p-type diffused layer 17 serving as an injector of the IIL and a p-type diffused layer 18 and p.sup.- -type diffused layer 12 serving as the base thereof are respectively so formed as to be adjoining to the oxide film 101 of the emitter lead-out portion of the IIL; and a p-type diffused layer 16 serving as the base of the vertical npn transistor is so formed as to be adjoining to the oxide film 101 of the collecter wall. The semiconductor device can achieve a smaller cell size, a decrease in parasitic capacitance and an increase in operating speed.

摘要翻译： 在具有垂直npn晶体管，集成在同一衬底上的垂直pnp晶体管和IIL的半导体器件中，到达用作IIL的发射极的n +型掩埋层5和n +型掩埋层4的沟槽 同时形成垂直npn晶体管的集电极，只在每个沟槽的侧壁上形成氧化膜101; 在凹槽中形成n +型多晶硅膜103和102，它们分别用作IIL的发射极引出部分和垂直npn晶体管的集电壁; 用作IIL的注射器的p型扩散层17和作为其基底的p型扩散层18和p型扩散层12分别形成为邻接于 发射极引出部分; 并且用作垂直npn晶体管的基极的p型扩散层16形成为与收集器壁的氧化物膜101相邻。 半导体器件可以实现更小的单元尺寸，寄生电容的减小和操作速度的增加。

公开(公告)号：US5696006A

公开(公告)日：1997-12-09

申请号：US691341

申请日：1996-08-02

申请人： Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

发明人： Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L29/51 ,  H01L21/265

CPC分类号： H01L29/513 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/518 ,  Y10S148/009

摘要： A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.

摘要翻译： 在硅衬底上形成氧化硅膜和多晶硅膜，并且被选择性地蚀刻以在要形成发射极的区域中形成接触孔。 将多晶硅膜放置在衬底上，并且将两个多晶硅膜图案化以形成由掺杂有砷的两个多晶硅膜制成的发射极电极和栅极电极。 砷从发射电极的多晶硅膜扩散到硅衬底中以形成具有高浓度且浅的N +发射极层。 因此，可以防止栅极绝缘膜的污染，并且可以形成具有高性能的双极晶体管，例如高电流放大因子等。

公开(公告)号：US5162252A

公开(公告)日：1992-11-10

申请号：US808691

申请日：1991-12-17

申请人： Akihiro Kanda ,  Mitsuo Tanaka ,  Takehiro Hirai ,  Masahiro Nakatani

发明人： Akihiro Kanda ,  Mitsuo Tanaka ,  Takehiro Hirai ,  Masahiro Nakatani

IPC分类号： H01L21/74 ,  H01L21/8226 ,  H01L21/8228 ,  H01L27/082

CPC分类号： H01L21/82285 ,  H01L21/743 ,  H01L21/8226 ,  H01L27/0826 ,  Y10S148/087

摘要： The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1). The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31).The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.

公开(公告)号：US4536950A

公开(公告)日：1985-08-27

申请号：US578036

申请日：1984-02-08

申请人： Hideaki Sadamatsu ,  Michihiro Inoue ,  Akihiro Kanda ,  Akira Matsuzawa

发明人： Hideaki Sadamatsu ,  Michihiro Inoue ,  Akihiro Kanda ,  Akira Matsuzawa

IPC分类号： H01L21/033 ,  H01L21/265 ,  H01L21/331 ,  H01L21/762 ,  H01L21/225

CPC分类号： H01L29/66272 ,  H01L21/033 ,  H01L21/2652 ,  H01L21/762

摘要： In making a vertical bipolar transistors, after forming by diffusion process a region to become inactive base region an oxide film is selectively formed on the region, thereafter an ion implantation is carried out to produce regions which become the active base region and emitter region by using the oxide film; thereby such a configuration is formed so that defect part (108) induced at the time of the ion implantation is confined in the emitter region, thereby minimizing the leakage current at the PN junction, and hence assuring production of high performance and high reliability semiconductor devices; further, a high integration is attained by adopting self-alignment in forming emitter contact.

摘要翻译： 在制造垂直双极晶体管时，在通过扩散处理成为非活性基极区域的区域之后，在该区域上选择性地形成氧化物膜，然后进行离子注入以通过使用成为有源基极区域和发射极区域的区域 氧化膜; 从而形成这样的结构，使得在离子注入时引起的缺陷部分（108）被限制在发射极区域中，从而使PN结处的漏电流最小化，从而确保生产高性能和高可靠性的半导体器件 ; 此外，通过在形成发射极接触中采用自对准来实现高集成度。

公开(公告)号：US5854535A

公开(公告)日：1998-12-29

申请号：US666398

申请日：1996-06-25

申请人： Andreas Hohlfeld ,  Dirk Hoffmann ,  Akihiro Kanda ,  Katsuya Otani

发明人： Andreas Hohlfeld ,  Dirk Hoffmann ,  Akihiro Kanda ,  Katsuya Otani

IPC分类号： H01J61/20 ,  H01J61/30 ,  H01J61/34

CPC分类号： H01J61/34 ,  H01J61/302

摘要： A metal halide lamp has an outer envelope (3, 23) of quartz glass which sounds a discharge vessel (2, 22) of quartz glass. The discharge vessel (2, 22) gas-tightly retains an ionizable fill which includes sodium. In order to avoid loss of sodium from the discharge vessel (2, 22) due to UV radiation impinging upon current supply wires (8, 9, 28, 29) extending from the discharge vessel (2, 22) within and into the outer envelope (3, 23), the quartz glass of the outer envelope is doped with materials absorbing UV radiation, preferably cerium aluminate and titanium oxide; the outer envelope is spaced from the discharge vessel by at most 5 mm, the sodium content in the ionizable fill is at most 0.7 mg.sup.3 of the discharge volume, and the space within the outer envelope is evacuated.

摘要翻译： PCT No.PCT / EP94 / 04233 371日期1996年6月25日第 102（e）日期1996年6月25日PCT 1994年12月20日PCT PCT。 出版物WO95 / 19639 日期1995年7月20日金属卤化物灯具有围绕石英玻璃的放电容器（2,22）的石英玻璃的外壳（3,23）。 放电容器（2,22）气密地保持包括钠的可电离填充物。 为了避免由于UV辐射照射在从放电容器（2,22）延伸并进入外封套的电源线（8,9,28,29）上而从放电容器（2,22）中的钠损失， （3,23），外壳的石英玻璃掺杂有吸收紫外线辐射的材料，优选铝酸铈和氧化钛; 外封套与放电容器隔开最多5mm，可离子化填充物中的钠含量至多为排放容积的0.7mg3，并且外封壳内的空间被抽空。