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    Processing unit containing DMA controller having concurrent operation with processor wherein addresses and data are divided into two parts
    2.
    发明授权
    Processing unit containing DMA controller having concurrent operation with processor wherein addresses and data are divided into two parts 失效
    具有与处理器并行操作的DMA控制器的处理单元，其中地址和数据被分成两部分

    公开(公告)号：US5136701A

    公开(公告)日：1992-08-04

    申请号：US725117

    申请日：1991-07-03

    申请人： Hiroyuki Kawai ,  Hideyuki Terane

    发明人： Hiroyuki Kawai ,  Hideyuki Terane

    IPC分类号： G06F13/28 ,  G06F13/36 ,  G06F15/78

    CPC分类号： G06F13/287

    摘要： A processing unit containing a DMA controller comprises a 2nb (n.gtoreq.1) processor data bus (6), a 2nb DMA data bus (7), a 2nb (m.gtoreq.1) processor address bus (8), and a 2nb DMA address bus (9). These buses have a plurality of latch circuits (51-54) respectively connected thereto. One of the processor and DMA data latched in each latch circuit, and one of the processor and DMA addresses are selected by a first multiplexer (55, 56). The 2nb data and 2mb data from the output of the first multiplexer and the outputs of the latch circuits are divided into sets of nb and mb, respectively; thus they are given in the form of 3 inputs to a second multiplixer (57-60). When the processor and the DMA controller concurrently operate, data and address are transferred without keeping one of them waiting.

    摘要翻译： 包含DMA控制器的处理单元包括2nb（n> / = 1）处理器数据总线（6），2nb DMA数据总线（7），2nb（m≥1）处理器地址总线（8）和 一个2nb DMA地址总线（9）。 这些总线具有分别与其连接的多个锁存电路（51-54）。 锁存在每个锁存电路中的处理器和DMA数据中的一个，并且处理器和DMA地址之一由第一多路复用器（55,56）选择。 来自第一多路复用器的输出的2nb数据和2mb数据以及锁存电路的输出分别分别为nb和mb; 因此它们以3个输入的形式被给予第二乘法器（57-60）。 当处理器和DMA控制器同时运行时，数据和地址被转移，而不保持其中一个等待。

    Direct memory access control device and method in a multiprocessor system accessing local and shared memory
    3.
    发明授权
    Direct memory access control device and method in a multiprocessor system accessing local and shared memory 失效
    直接存储器访问控制设备和方法在多处理器系统中访问本地和共享内存

    公开(公告)号：US5584010A

    公开(公告)日：1996-12-10

    申请号：US358670

    申请日：1994-12-19

    申请人： Hiroyuki Kawai ,  Hideyuki Terane

    发明人： Hiroyuki Kawai ,  Hideyuki Terane

    IPC分类号： G06F15/16 ,  G06F13/28 ,  G06F13/38 ,  G06F15/163 ,  G06F13/40 ,  G06F12/08 ,  G06F13/36

    CPC分类号： G06F13/28

    摘要： A direct memory access control device is used in a multiprocessor system having a plurality of digital data processors and an external common memory connected in common to those digital data processors through a first bus. In the case of transferring data in a direct memory access mode between processors, the transfer of data between the processors is effected by the control device through a second data bus provided in common to the plurality of digital data processors separately from the first bus. Thus, data can be transferred directly in a direct memory access mode between the processors without using the external memory and high-speed transfer can be realized. In addition, the control device comprises registers for storing the status bits of each digital data processor, such as direct memory access request and acceptance signals, corresponding to each digital data processor. Request and acceptance of direct memory access and transfer of data are effected by monitoring the contents of those registers.

    摘要翻译： 直接存储器访问控制装置用于具有多个数字数据处理器和通过第一总线与这些数字数据处理器共同连接的外部公共存储器的多处理器系统。 在处理器之间以直接存储器访问模式传送数据的情况下，处理器之间的数据传输由控制设备通过与第一总线分离地与多个数字数据处理器共同提供的第二数据总线来实现。 因此，可以在处理器之间的直接存储器访问模式中直接传送数据，而不使用外部存储器，并且可以实现高速传输。 此外，控制装置包括用于存储每个数字数据处理器的状态位的寄存器，例如对应于每个数字数据处理器的直接存储器访问请求和接收信号。 通过监视这些寄存器的内容来实现对存储器直接访问和数据传输的请求和接受。

    SR latch circuit
    4.
    发明授权
    SR latch circuit 失效
    SR锁存电路

    公开(公告)号：US5051610A

    公开(公告)日：1991-09-24

    申请号：US456335

    申请日：1989-12-26

    申请人： Hideyuki Terane ,  Hiroyuki Kawai

    发明人： Hideyuki Terane ,  Hiroyuki Kawai

    IPC分类号： H03K3/356 ,  H03K3/037

    CPC分类号： H03K3/037

    摘要： An SR latch is provided, which comprises a D-type latch and a logic circuit connected between data and sense input of the D-type latch and set and reset input terminals of the SR latch circuit. The logic circuit establishes the logic levels of signals applied to the data and sense inputs of the D-type latch such that said SR latch circit can assume one of set, reset and hold states depending on the combination of the logic levels of the signals applied to the set and reset input terminals.

    摘要翻译： 提供SR锁存器，其包括D型锁存器和连接在D型锁存器的数据和检测输入之间的逻辑电路以及SR锁存器电路的设置和复位输入端子。 逻辑电路建立施加到数据的信号的逻辑电平并且感测D型锁存器的输入，使得所述SR锁存器环路可以根据施加的信号的逻辑电平的组合来采取设置，复位和保持状态之一 到设置和复位输入端子。

    Separator for alkaline battery, method for producing the same, and battery
    6.
    发明授权
    Separator for alkaline battery, method for producing the same, and battery 有权
    碱性电池用隔膜，其制造方法以及电池

    公开(公告)号：US08865336B2

    公开(公告)日：2014-10-21

    申请号：US12517840

    申请日：2007-12-07

    申请人： Tomohiro Hayakawa ,  Shinya Inada ,  Hideo Hayashi ,  Hiroyuki Kawai ,  Masakazu Nishiyama

    发明人： Tomohiro Hayakawa ,  Shinya Inada ,  Hideo Hayashi ,  Hiroyuki Kawai ,  Masakazu Nishiyama

    IPC分类号： H01M2/16 ,  H01M2/14

    CPC分类号： H01M2/162 ,  H01M2/145 ,  H01M2/1626 ,  H01M2/1653 ,  H01M2/1686 ,  Y02E60/12 ,  Y10S977/948

    摘要： Provided is a separator for alkaline batteries which can not only prevent batteries from internal short circuit by inhibiting the dendrite formation at anode, but also enables to have a low electrical resistance. The separator for alkaline batteries comprises a composite sheet in which a base layer comprising a wet-type nonwoven material formed from alkaline resistant fibers is covered with a nanofiber layer comprising a modified polyvinyl alcohol fiber which has a fiber diameter of 10 to 1000 nm and a liquid absorption amount by fibers of 4.0 to 40.0 g/g after immersion in a 35% aqueous solution of KOH.

    摘要翻译： 本发明提供一种碱性电池用隔膜，其不仅能够通过抑制阳极中的枝晶形成来防止电池内部短路，还能够具有低的电阻。 用于碱性电池的隔板包括复合片，其中包含由耐碱性纤维形成的湿式非织造材料的基层被纳米纤维层覆盖，所述纳米纤维层包含纤维直径为10至1000nm的改性聚乙烯醇纤维和 在35％的KOH水溶液中浸渍后，纤维的液体吸收量为4.0〜40.0g / g。

    ALKALINE BATTERY SEPARATOR AND ALKALINE BATTERY USING SEPARATOR
    7.
    发明申请
    ALKALINE BATTERY SEPARATOR AND ALKALINE BATTERY USING SEPARATOR 有权
    碱性电池分离器和使用分离器的碱性电池

    公开(公告)号：US20130183569A1

    公开(公告)日：2013-07-18

    申请号：US13823128

    申请日：2011-09-06

    申请人： Tomohiro Hayakawa ,  Koichi Kambe ,  Hiroyuki Kawai

    发明人： Tomohiro Hayakawa ,  Koichi Kambe ,  Hiroyuki Kawai

    IPC分类号： H01M2/16

    CPC分类号： H01M2/1626 ,  H01M2/1613 ,  H01M2/1633 ,  H01M2/1686 ,  H01M10/24

    摘要： Provided are an alkaline battery separator and an alkaline battery including the separator. The separator includes at least a coarse layer and a dense layer denser than the coarse layer. The coarse layer contains an alkaline-resistant cellulose fiber having a freeness value of 350 to 650 ml as a whole in the proportion of 25 to 65% by weight. The alkaline-resistant cellulose fiber includes at least two kinds of alkaline-resistant cellulose fibers having different freeness with each other. The difference in freeness value between the alkaline-resistant cellulose fibers having the highest and lowest freeness values is 300 to 700 ml. The dense layer contains an alkaline-resistant cellulose fiber which as a whole has a freeness value of 0 to 400 ml. The separator has a maximum pore size of 65 μm or smaller, and a liquid absorption capacity of 5 g/g or higher.

    摘要翻译： 提供了一种碱性电池隔板和包括隔膜的碱性电池。 分离器至少包括粗糙层和比粗糙层更致密的致密层。 该粗糙层含有比例为25〜65重量％的游离度350〜650ml的耐碱性纤维素纤维。 耐碱性纤维素纤维包含至少两种互不相同游离度的耐碱性纤维素纤维。 具有最高和最低游离度值的耐碱性纤维素纤维之间的游离度差值为300至700ml。 致密层含有耐碱纤维素纤维，整体上其游离度为0-400ml。 隔膜的最大孔径为65μm以下，液体吸收容量为5g / g以上。

    MIMO multiplexing communication system and a signal separation method
    9.
    发明授权
    MIMO multiplexing communication system and a signal separation method 失效
    MIMO复用通信系统和信号分离方法

    公开(公告)号：US07864897B2

    公开(公告)日：2011-01-04

    申请号：US11909607

    申请日：2006-03-20

    申请人： Noriyuki Maeda ,  Hiroyuki Kawai ,  Kenichi Higuchi ,  Mamoru Sawahashi

    发明人： Noriyuki Maeda ,  Hiroyuki Kawai ,  Kenichi Higuchi ,  Mamoru Sawahashi

    IPC分类号： H04L27/06 ,  H04L23/02

    CPC分类号： H04B7/0413 ,  H04L25/0204 ,  H04L25/0228 ,  H04L25/0246 ,  H04L25/03191 ,  H04L25/03242 ,  H04L2025/03426

    摘要： A disclosed receiver in a MIMO multiplexing communication system, in which plural signals are simultaneously transmitted from plural transmitting antenna branches using the same frequency, and the transmitted signals are retrieved by receiving signals at plural receiving antennas, separating the received signals and searching for proper symbol metrics for each branch, comprises a QR decomposer for QR decomposing the received signals to orthogonalize the transmitted signals; a symbol replica candidate ranking unit for subtracting surviving symbol replica candidates from the QR decomposed received signals to get remaining received signals and rank the remaining signals in the increasing order of expected branch metrics of the remaining received signals; a symbol replica candidate selector for selecting symbol replica candidates in the ranked order; a branch metric calculator for calculating the branch metrics of the selected symbol replica candidates; and a threshold comparator for comparing the calculated branch metrics with a predetermined threshold; wherein if a calculated branch metric is larger than the predetermined threshold, the branch metric and successive branch metrics are deleted without further searching.

    摘要翻译： 在MIMO复用通信系统中公开的接收机，其中使用相同频率从多个发送天线分支同时发送多个信号，并且通过在多个接收天线处接收信号来检索所发送的信号，分离接收的信号并搜索适当的符号 每个分支的度量包括QR分解器，用于QR分解接收的信号以使发送的信号正交化; 符号复制候选排​​序单元，用于从所述QR分解的接收信号中减去剩余码元复制候选，以获得剩余的接收信号，并以剩余接收信号的预期分支度量的递增顺序对剩余信号进行排序; 用于以排序顺序选择符号复本候选者的符号复制候选选择器; 分支度量计算器，用于计算所选择的符号复本候选的分支度量; 以及阈值比较器，用于将所计算的分支度量与预定阈值进行比较; 其中如果所计算的分支度量大于所述预定阈值，则所述分支度量和连续分支度量被删除而不进一步搜索。

    BASE STATION APPARATUS, USER APPARATUS AND COMMUNICATION CONTROL METHOD
    10.
    发明申请
    BASE STATION APPARATUS, USER APPARATUS AND COMMUNICATION CONTROL METHOD 审中-公开
    基站装置，用户装置和通信控制方法

    公开(公告)号：US20100254326A1

    公开(公告)日：2010-10-07

    申请号：US12680414

    申请日：2008-09-26

    申请人： Mamoru Sawahashi ,  Hiroyuki Kawai

    发明人： Mamoru Sawahashi ,  Hiroyuki Kawai

    IPC分类号： H04W72/04

    CPC分类号： H04B7/02 ,  H04B7/0604 ,  H04B7/061 ,  H04J11/0069 ,  H04L5/0023 ,  H04L5/0037 ,  H04L5/006

    摘要： The user apparatus is provided with a plurality of antennas, and transmits a reference signal in the uplink by switching the plurality of antennas. The plurality of antennas are associated with subframes transmitted in the uplink. The base station apparatus in a radio communication system to which transmission diversity is applied in the uplink includes: a reception level storing unit configured to store a measured reception level of the reference signal for each antenna of each user apparatus; and a scheduler configured to perform, based on the reception level of the reference signal transmitted for each antenna of each user apparatus stored in the reception level storing unit, scheduling for determining a user apparatus to be assigned to a subframe associated with the antenna.

    摘要翻译： 用户装置设置有多个天线，并且通过切换多个天线来在上行链路中发送参考信号。 多个天线与在上行链路中发送的子帧相关联。 在上行链路中应用了发送分集的无线通信系统中的基站装置包括：接收电平存储部，被配置为存储每个用户装置的每个天线的基准信号的测定接收电平; 以及调度器，被配置为基于对存储在接收电平存储单元中的每个用户装置的每个天线发送的参考信号的接收电平执行用于确定要分配给与天线相关联的子帧的用户装置的调度。