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公开(公告)号：US07068584B2
公开(公告)日：2006-06-27
申请号：US10376247
申请日：2003-03-03
申请人： Hiroki Mouri , Hiroyuki Nakahira , Akira Yamamoto
发明人： Hiroki Mouri , Hiroyuki Nakahira , Akira Yamamoto
IPC分类号： G11B7/00
CPC分类号： G11B20/10046 , G11B20/10009 , G11B20/10296
摘要： The signal processor includes an analog filter, an analog-to-digital (A-D) converter, an adaptive equalization filter, a quality value calculating circuit, and a control circuit. The analog filter removes high-frequency noises of a played-back signal from a recording medium and amplifies a specific frequency band of the played-back signal. The A-D converter converts the played-back signal from the analog filter into a digital signal. The adaptive equalization filter performs waveform equalization of the played-back signal from the A-D converter while adjusting a tap coefficient of the adaptive equalization filter so as to reduce a difference between an output of the adaptive equalization filter and a target value. The quality value calculating circuit calculates a quality value based on the difference between the output of the adaptive equalization filter and the target value. The control circuit compares the quality value calculated by the quality value calculating circuit with a predetermined reference value, and conducts a process for improving the quality value according to the comparison result.
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公开(公告)号：US06778483B2
公开(公告)日：2004-08-17
申请号：US09984768
申请日：2001-10-31
IPC分类号： G11B576
CPC分类号： G11B20/10009 , G11B20/1488 , H03M5/16 , H04L25/4923
摘要： An encoding efficiency higher than 1 is achieved by accomplishing ternary recording on a recording medium. For this purpose, an 8-bit binary data word is converted to a 5-symbol ternary code word. A look-up table stores a modulation/demodulation table defining the correspondence between the binary data word (8B) and the ternary code word (5T). A table generating circuit generates the modulation/demodulation table to be stored in the look-up table such that each of constraints specified by a plurality of parameters is satisfied. If a PRML (Partial Response Maximum Likelihood) scheme is combined with an 8B5T code thus obtained, a signal-to-noise ratio is improved.
摘要翻译： 通过在记录介质上进行三进制记录来实现高于1的编码效率。 为此，将8位二进制数据字转换为5符号三进制码字。 查找表存储定义二进制数据字（8B）和三进制码字（5T）之间的对应关系的调制/解调表。 表生成电路生成要存储在查找表中的调制/解调表，使得满足由多个参数指定的每个约束。 如果PRML（部分响应最大似然）方案与由此获得的8B5T码组合，则提高了信噪比。
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公开(公告)号：US06745218B1
公开(公告)日：2004-06-01
申请号：US09527404
申请日：2000-03-16
IPC分类号： G06F1710
CPC分类号： H03H21/0012
摘要： An adaptive digital filter of the present invention includes: a pipelined filtering section for performing a filtering operation based on input data and coefficient data so as to output filtered data; and a non-pipelined adaptation section for outputting the coefficient data to the pipelined filtering section by performing a coefficient adaptation operation in a non-pipelined process based on the input data and the filtered data so that the filtered data output from the pipelined filtering section converges to a predetermined reference value.
摘要翻译： 本发明的自适应数字滤波器包括：流水线滤波部分，用于基于输入数据和系数数据执行滤波操作，以便输出滤波数据; 以及非流水线自适应部分，用于基于输入数据和滤波数据，通过在非流水线处理中执行系数自适应操作，将系数数据输出到流水线过滤部分，使得从流水线过滤部分输出的滤波数据收敛 到预定的参考值。
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公开(公告)号：US20050270677A1
公开(公告)日：2005-12-08
申请号：US11198950
申请日：2005-08-08
CPC分类号： G11B20/10 , G11B5/09 , G11B20/10194 , G11B20/10212 , G11B2005/0005 , H03K5/082 , H03K5/13 , H03K5/133
摘要： A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.
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5.发明授权Write compensation circuit and signal interpolation circuit of recording device 有权写记录装置的补偿电路和信号插补电路公开(公告)号：US07523154B2
公开(公告)日：2009-04-21
申请号：US11198950
申请日：2005-08-08
IPC分类号： G06G7/00
CPC分类号： G11B20/10 , G11B5/09 , G11B20/10194 , G11B20/10212 , G11B2005/0005 , H03K5/082 , H03K5/13 , H03K5/133
摘要： A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.
摘要翻译： 记录装置的写补偿电路包括由第一驱动电压驱动的第一延迟部分，用于接收时钟信号，延迟时钟信号第一延迟时间，并输出延迟时钟信号;以及电压提供部分，用于提供 第一驱动电压到第一延迟部分，使得第一延迟时间基本上等于时钟信号的时钟周期。
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6.发明授权Write compensation circuit and signal interpolation circuit of recording device 失效写记录装置的补偿电路和信号插补电路公开(公告)号：US06970313B1
公开(公告)日：2005-11-29
申请号：US09539206
申请日：2000-03-30
CPC分类号： G11B20/10 , G11B5/09 , G11B20/10194 , G11B20/10212 , G11B2005/0005 , H03K5/082 , H03K5/13 , H03K5/133
摘要： A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.
摘要翻译： 记录装置的写补偿电路包括由第一驱动电压驱动的第一延迟部分，用于接收时钟信号，延迟时钟信号第一延迟时间，并输出延迟时钟信号;以及电压提供部分，用于提供 第一驱动电压到第一延迟部分，使得第一延迟时间基本上等于时钟信号的时钟周期。
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7.发明授权Timing extractor, and information playback apparatus and DVD device using the timing extractor 有权定时提取器，信息播放装置和使用定时提取器的DVD装置公开(公告)号：US07688687B2
公开(公告)日：2010-03-30
申请号：US11667299
申请日：2006-07-18
申请人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri
发明人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri
IPC分类号： G11B7/085
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10222 , G11B20/1403 , G11B2020/1476 , G11B2220/2562 , H03L7/091 , H03L7/1976 , H04L7/02 , H04L7/033
摘要： In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation section 2 calculates the ratio between the frequency of the playback signal and the frequency of the output clock of a frequency synthesizer 6 by utilizing a specific pattern and a specific pattern appearing interval in the playback signal. A control section 4 controls the frequency dividing rate of the frequency synthesizer 6 in such a manner that the frequency ratio calculated by the frequency ratio calculation section 2 has a set value. Thus, as compared with a case in which the output clock of the frequency synthesizer 6 is a high-frequency fixed-rate clock, it is not necessary to operate the digital circuits at high speeds. Consequently, even in cases where the playback frequency (the playback rate) of the signal changes with time, the decimation rate at which pulses of a fixed clock are eliminated is constant, thereby reducing power consumption.
摘要翻译： 在从再现信号中提取定时信息的前馈定时提取器中，频率比计算部分2通过利用特定的模式和特定的模式来计算重放信号的频率与频率合成器6的输出时钟的频率之间的比率 重放信号中的图案出现间隔。 控制部分4以频率比计算部分2计算出的频率比具有设定值的方式控制频率合成器6的分频率。 因此，与频率合成器6的输出时钟为高频固定速度时钟的情况相比，不需要以高速操作数字电路。 因此，即使在信号的重放频率（播放速度）随时间变化的情况下，消除固定时钟的脉冲的抽取率恒定，从而降低功耗。
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公开(公告)号：US20100020250A1
公开(公告)日：2010-01-28
申请号：US12526746
申请日：2007-11-01
CPC分类号： H04L7/0331 , G11B20/10009 , G11B20/10037 , G11B20/10222 , G11B20/14 , G11B2020/1287 , G11B2220/2541 , G11B2220/2545 , G11B2220/2562 , H03L7/06
摘要： In a feedforward control type reproduced signal processor, a clock generator 1 changes a clock frequency, depending on a digital value set by a digital value generator 7. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculator 3 satisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator 1. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generator 1 gradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.
摘要翻译： 在前馈控制型再现信号处理器中，时钟发生器1根据由数字值发生器7设定的数字值改变时钟频率。因此，优化了系统的功耗并且便于控制。 此外，当频率锁定状态被建立，其中由频率比计算器3计算的频率比满足设定条件时，使用时钟发生器1的时钟产生具有小变化的调制分量。因此，数字值为 用调制分量更新，使得时钟发生器1的时钟频率的变化逐渐变化。 结果，降低了时钟频率的变化对解码处理的响应的影响。
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公开(公告)号：US20080253011A1
公开(公告)日：2008-10-16
申请号：US10587080
申请日：2005-01-06
申请人： Hiroki Mouri , Akira Yamamoto
发明人： Hiroki Mouri , Akira Yamamoto
IPC分类号： G11B5/09
CPC分类号： H04L25/497 , G11B20/10009 , G11B20/10055 , H03L7/091 , H03L7/093 , H04L7/033 , H04L25/03019 , H04L25/03178
摘要： There is provided a signal processing apparatus and a signal processing method, which can simultaneously perform reduction in jitter components and reduction in error rate.A signal processing apparatus for processing a signal by a PRML method is provided with an A/D converter (4) for converting an analog signal into a digital signal; a first waveform equalizer (14) which is connected to the A/D converter (4), and amplifies a specific band of a signal to optimize data of a clock extraction system; a second waveform equalizer (15) which is connected to the A/D converter (4), and amplifies the specific band of the signal and performs waveform equalization to optimize data of a data processing system; a timing recovery logic circuit (11) which is connected to the first waveform equalizer (14), and extracts a reproduction clock; and a decoder (16) which is connected to the second waveform equalizer (15), and decodes data.
摘要翻译： 提供了一种信号处理装置和信号处理方法，其可以同时执行抖动分量的降低和误码率的降低。 用于通过PRML方法处理信号的信号处理装置设置有用于将模拟信号转换为数字信号的A / D转换器（4） 第一波形均衡器（14），其连接到A / D转换器（4），并放大信号的特定频带以优化时钟提取系统的数据; 连接到A / D转换器（4）的第二波形均衡器（15），放大信号的特定频带并执行波形均衡以优化数据处理系统的数据; 定时恢复逻辑电路（11），连接到第一波形均衡器（14），并提取再现时钟; 以及连接到第二波形均衡器（15）的解码器（16），并对数据进行解码。
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公开(公告)号：US08098972B2
公开(公告)日：2012-01-17
申请号：US12526746
申请日：2007-11-01
CPC分类号： H04L7/0331 , G11B20/10009 , G11B20/10037 , G11B20/10222 , G11B20/14 , G11B2020/1287 , G11B2220/2541 , G11B2220/2545 , G11B2220/2562 , H03L7/06
摘要： In a feedforward control type reproduced signal processor, a clock generator 1 changes a clock frequency, depending on a digital value set by a digital value generator 7. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculator 3 satisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator 1. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generator 1 gradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.
摘要翻译： 在前馈控制型再现信号处理器中，时钟发生器1根据由数字值发生器7设定的数字值改变时钟频率。因此，优化了系统的功耗并且便于控制。 此外，当频率锁定状态被建立，其中由频率比计算器3计算的频率比满足设定条件时，使用时钟发生器1的时钟产生具有小变化的调制分量。因此，数字值为 用调制分量更新，使得时钟发生器1的时钟频率的变化逐渐变化。 结果，降低了时钟频率的变化对解码处理的响应的影响。
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