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21 条记录 (耗时 0.024 秒)

    Multilevel record modulator and demodulator
    1.
    发明授权
    Multilevel record modulator and demodulator 失效
    多级记录调制器和解调器

    公开(公告)号：US06778483B2

    公开(公告)日：2004-08-17

    申请号：US09984768

    申请日：2001-10-31

    申请人： Hiroki Mouri ,  Takashi Yamamoto ,  Hiroyuki Nakahira ,  Akira Yamamoto

    发明人： Hiroki Mouri ,  Takashi Yamamoto ,  Hiroyuki Nakahira ,  Akira Yamamoto

    IPC分类号： G11B576

    CPC分类号： G11B20/10009 ,  G11B20/1488 ,  H03M5/16 ,  H04L25/4923

    摘要： An encoding efficiency higher than 1 is achieved by accomplishing ternary recording on a recording medium. For this purpose, an 8-bit binary data word is converted to a 5-symbol ternary code word. A look-up table stores a modulation/demodulation table defining the correspondence between the binary data word (8B) and the ternary code word (5T). A table generating circuit generates the modulation/demodulation table to be stored in the look-up table such that each of constraints specified by a plurality of parameters is satisfied. If a PRML (Partial Response Maximum Likelihood) scheme is combined with an 8B5T code thus obtained, a signal-to-noise ratio is improved.

    摘要翻译： 通过在记录介质上进行三进制记录来实现高于1的编码效率。 为此，将8位二进制数据字转换为5符号三进制码字。 查找表存储定义二进制数据字（8B）和三进制码字（5T）之间的对应关系的调制/解调表。 表生成电路生成要存储在查找表中的调制/解调表，使得满足由多个参数指定的每个约束。 如果PRML（部分响应最大似然）方案与由此获得的8B5T码组合，则提高了信噪比。

    Signal processor
    2.
    发明授权
    Signal processor 失效

    公开(公告)号：US07068584B2

    公开(公告)日：2006-06-27

    申请号：US10376247

    申请日：2003-03-03

    申请人： Hiroki Mouri ,  Hiroyuki Nakahira ,  Akira Yamamoto

    发明人： Hiroki Mouri ,  Hiroyuki Nakahira ,  Akira Yamamoto

    IPC分类号： G11B7/00

    CPC分类号： G11B20/10046 ,  G11B20/10009 ,  G11B20/10296

    摘要： The signal processor includes an analog filter, an analog-to-digital (A-D) converter, an adaptive equalization filter, a quality value calculating circuit, and a control circuit. The analog filter removes high-frequency noises of a played-back signal from a recording medium and amplifies a specific frequency band of the played-back signal. The A-D converter converts the played-back signal from the analog filter into a digital signal. The adaptive equalization filter performs waveform equalization of the played-back signal from the A-D converter while adjusting a tap coefficient of the adaptive equalization filter so as to reduce a difference between an output of the adaptive equalization filter and a target value. The quality value calculating circuit calculates a quality value based on the difference between the output of the adaptive equalization filter and the target value. The control circuit compares the quality value calculated by the quality value calculating circuit with a predetermined reference value, and conducts a process for improving the quality value according to the comparison result.

    Adaptive digital filter
    6.
    发明授权
    Adaptive digital filter 失效
    自适应数字滤波器

    公开(公告)号：US06745218B1

    公开(公告)日：2004-06-01

    申请号：US09527404

    申请日：2000-03-16

    申请人： Akira Yamamoto ,  Hiroyuki Nakahira ,  Hirokuni Fujiyama ,  Hiroki Mouri

    发明人： Akira Yamamoto ,  Hiroyuki Nakahira ,  Hirokuni Fujiyama ,  Hiroki Mouri

    IPC分类号： G06F1710

    CPC分类号： H03H21/0012

    摘要： An adaptive digital filter of the present invention includes: a pipelined filtering section for performing a filtering operation based on input data and coefficient data so as to output filtered data; and a non-pipelined adaptation section for outputting the coefficient data to the pipelined filtering section by performing a coefficient adaptation operation in a non-pipelined process based on the input data and the filtered data so that the filtered data output from the pipelined filtering section converges to a predetermined reference value.

    摘要翻译： 本发明的自适应数字滤波器包括：流水线滤波部分，用于基于输入数据和系数数据执行滤波操作，以便输出滤波数据; 以及非流水线自适应部分，用于基于输入数据和滤波数据，通过在非流水线处理中执行系数自适应操作，将系数数据输出到流水线过滤部分，使得从流水线过滤部分输出的滤波数据收敛 到预定的参考值。

    Optical Disc Device
    7.
    发明申请
    Optical Disc Device 审中-公开
    光盘设备

    公开(公告)号：US20080101176A1

    公开(公告)日：2008-05-01

    申请号：US11794228

    申请日：2005-10-20

    申请人： Hiroki Mouri ,  Hiroyuki Nakahira ,  Kouichi Nagano

    发明人： Hiroki Mouri ,  Hiroyuki Nakahira ,  Kouichi Nagano

    IPC分类号： G11B7/00

    CPC分类号： G11B7/00456 ,  G11B7/0045 ,  G11B7/126 ,  G11B20/10009 ,  G11B20/10222 ,  G11B20/10425 ,  G11B20/1403 ,  G11B2220/2537 ,  H03K5/135

    摘要： There has been an issue that the operation of a semiconductor circuit performing edge timing control cannot follow up in the multipulse generation process where high multiplication of speed progresses every year. A light strategy drive comprises a control register (22) storing timing edge information for generating the edge of a recording waveform signal, a PLL (23) generating a clock for generating the edge of a recording waveform signal, and a timing control circuit (24) for receiving timing edge information corresponding to the recording waveform signal from the control register (22) to output timing edge information having a predetermined amount of delay in parallel and compounding the edges based on the timing edge information outputted in parallel. Timing edge can be controlled with high precision even at the time of high speed operation, and a high precision multipulse can be generated.

    摘要翻译： 存在这样的问题，即，进行边缘定时控制的半导体电路的动作不能随着速度的高乘法每年进行的多脉冲生成处理而跟随。 光策略驱动器包括存储用于产生记录波形信号的边缘的定时边缘信息的控制寄存器（22），产生用于产生记录波形信号的边缘的时钟的PLL（23）和定时控制电路（24 ），用于接收与来自控制寄存器（22）的记录波形信号相对应的定时边缘信息，以基于并行输出的定时边缘信息并行输出具有预定延迟量的定时边缘信息并使边缘复合。 即使在高速运转时，也可以高精度地控制定时边缘，能够产生高精度的多脉冲。

    Timing extraction device and video display device
    8.
    发明授权
    Timing extraction device and video display device 失效
    定时提取装置和视频显示装置

    公开(公告)号：US08270269B2

    公开(公告)日：2012-09-18

    申请号：US11918236

    申请日：2005-11-11

    申请人： Hiroki Mouri ,  Akira Yamamoto

    发明人： Hiroki Mouri ,  Akira Yamamoto

    IPC分类号： G11B5/09

    CPC分类号： H04L7/04 ,  G11B20/10009 ,  G11B2020/1287

    摘要： An asynchronous timing detector 3 detects and measures a specific pattern (sync pattern) of audio and video reproduced signals having a digital value form an A/D converter 2 and its appearance interval based on an asynchronous clock generated by an asynchronous clock generator 4, and calculates a cycle ratio of the measured sync pattern appearance interval (the number of clock pulses of the asynchronous clock) to a normal value (the number of clock pulses of a synchronous clock obtained by measuring a sync pattern appearance interval using the synchronous clock). A pseudo-synchronous clock generator 7 thins the asynchronous clock based on the cycle ratio to generate a pseudo-synchronous clock which is pseudo-synchronous with channel data. Therefore, even when an initial frequency error is large, frequency and phase pull-in is relatively quickly performed until a timing recovery operation becomes stable.

    摘要翻译： 异步定时检测器3基于由异步时钟发生器4产生的异步时钟来检测并测量具有A / D转换器2的数字值的音频和视频再现信号的特定模式（同步模式）及其出现间隔，以及 将所测量的同步图形显示间隔（异步时钟的时钟脉冲数）的周期比计算到正常值（通过使用同步时钟测量同步模式出现间隔而获得的同步时钟的时钟脉冲数）。 伪同步时钟发生器7基于该周期比使该异步时钟产生一个与通道数据伪同步的伪同步时钟。 因此，即使在初始频率误差大的情况下，相对快速地执行频率和相位拉入，直到定时恢复操作变得稳定。

    Timing extractor, and information playback apparatus and dvd device using the timing extractor
    9.
    发明申请
    Timing extractor, and information playback apparatus and dvd device using the timing extractor 有权
    定时提取器，以及使用定时提取器的信息播放装置和DVD设备

    公开(公告)号：US20090086588A1

    公开(公告)日：2009-04-02

    申请号：US11667299

    申请日：2006-07-18

    申请人： Kouji Okamoto ,  Akira Yamamoto ,  Hiroki Mouri

    发明人： Kouji Okamoto ,  Akira Yamamoto ,  Hiroki Mouri

    IPC分类号： G11B21/08

    CPC分类号： G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/1403 ,  G11B2020/1476 ,  G11B2220/2562 ,  H03L7/091 ,  H03L7/1976 ,  H04L7/02 ,  H04L7/033

    摘要： In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation section 2 calculates the ratio between the frequency of the playback signal and the frequency of the output clock of a frequency synthesizer 6 by utilizing a specific pattern and a specific pattern appearing interval in the playback signal. A control section 4 controls the frequency dividing rate of the frequency synthesizer 6 in such a manner that the frequency ratio calculated by the frequency ratio calculation section 2 has a set value. Thus, as compared with a case in which the output clock of the frequency synthesizer 6 is a high-frequency fixed-rate clock, it is not necessary to operate the digital circuits at high speeds. Consequently, even in cases where the playback frequency (the playback rate) of the signal changes with time, the decimation rate at which pulses of a fixed clock are eliminated is constant, thereby reducing power consumption.

    摘要翻译： 在从再现信号中提取定时信息的前馈定时提取器中，频率比计算部分2通过利用特定的模式和特定的模式来计算重放信号的频率与频率合成器6的输出时钟的频率之间的比率 重放信号中的图案出现间隔。 控制部分4以频率比计算部分2计算出的频率比具有设定值的方式控制频率合成器6的分频率。 因此，与频率合成器6的输出时钟为高频固定速度时钟的情况相比，不需要以高速操作数字电路。 因此，即使在信号的重放频率（播放速度）随时间变化的情况下，消除固定时钟的脉冲的抽取率恒定，从而降低功耗。

    Timing Extraction Device and Video Display Device
    10.
    发明申请
    Timing Extraction Device and Video Display Device 失效
    定时提取设备和视频显示设备

    公开(公告)号：US20090060451A1

    公开(公告)日：2009-03-05

    申请号：US11918236

    申请日：2005-11-11

    申请人： Hiroki Mouri ,  Akira Yamamoto

    发明人： Hiroki Mouri ,  Akira Yamamoto

    IPC分类号： H04N5/95 ,  G11B20/10

    CPC分类号： H04L7/04 ,  G11B20/10009 ,  G11B2020/1287

    摘要： An asynchronous timing detector 3 detects and measures a specific pattern (sync pattern) of audio and video reproduced signals having a digital value form an A/D converter 2 and its appearance interval based on an asynchronous clock generated by an asynchronous clock generator 4, and calculates a cycle ratio of the measured sync pattern appearance interval (the number of clock pulses of the asynchronous clock) to a normal value (the number of clock pulses of a synchronous clock obtained by measuring a sync pattern appearance interval using the synchronous clock). A pseudo-synchronous clock generator 7 thins the asynchronous clock based on the cycle ratio to generate a pseudo-synchronous clock which is pseudo-synchronous with channel data. Therefore, even when an initial frequency error is large, frequency and phase pull-in is relatively quickly performed until a timing recovery operation becomes stable.

    摘要翻译： 异步定时检测器3基于由异步时钟发生器4产生的异步时钟来检测并测量具有A / D转换器2的数字值的音频和视频再现信号的特定模式（同步模式）及其出现间隔，以及 将所测量的同步图形显示间隔（异步时钟的时钟脉冲数）的周期比计算到正常值（通过使用同步时钟测量同步模式出现间隔而获得的同步时钟的时钟脉冲数）。 伪同步时钟发生器7基于该周期比使该异步时钟产生一个与通道数据伪同步的伪同步时钟。 因此，即使在初始频率误差大的情况下，相对快速地执行频率和相位拉入，直到定时恢复操作变得稳定。