公开(公告)号：US5515187A

公开(公告)日：1996-05-07

申请号：US45764

申请日：1993-04-14

申请人： Hiroki Nakamura ,  Youichi Masuda

发明人： Hiroki Nakamura ,  Youichi Masuda

IPC分类号： G02F1/1362 ,  G09G3/36 ,  G02F1/1343

CPC分类号： G02F1/136213 ,  G09G3/3648

摘要： A liquid crystal display is described which comprises a plurality of switching elements each including an active region disposed between a drain region and a source region, a pair of pixel elements respectively connected to the drain regions of switching elements, a signal line connecting between a signal line driving circuit and the drain region of the switching element and being disposed between the pair of the pixel elements, a storage capacitor line including a portion disposed between the pair of the pixel elements, and a first dielectric layer interposed between the signal line and the storage capacitor line portion.

摘要翻译： 描述了一种液晶显示器，其包括多个开关元件，每个开关元件包括设置在漏极区域和源极区域之间的有源区域，分别连接到开关元件的漏极区域的一对像素元件，连接在开关元件的信号线之间的信号线 线路驱动电路和开关元件的漏极区域，并且设置在所述一对像素元件之间;辅助电容器线，包括设置在所述一对像素元件之间的部分，以及插入在所述一对像素元件之间的第一介电层， 存储电容器线部分。

公开(公告)号：US6107983A

公开(公告)日：2000-08-22

申请号：US41950

申请日：1998-03-13

申请人： Youichi Masuda ,  Nozomu Harada ,  Hiroki Nakamura

发明人： Youichi Masuda ,  Nozomu Harada ,  Hiroki Nakamura

IPC分类号： G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2310/021 ,  G09G2310/0224 ,  G09G2310/0232 ,  G09G2310/0283 ,  G09G2330/021 ,  G09G2330/08 ,  G09G2340/0407 ,  G09G2340/0471 ,  G09G2340/0478 ,  G09G2340/0485 ,  G09G3/2011

摘要： A display device comprises a display panel, a scanning circuit section for supplying a scanning signal to scanning lines of the display panel, and a scanning control circuit section for supplying an n-bit (n: 2 or more positive integer) input numeral signal and an inverted replica of the input numeral signal to the scanning circuit section. In the display device, a scanning circuit section comprises an input connection line group having sets of input connection lines for receiving bits of the input numeral signal and bits of the inverted replica of the input numeral signal, a plurality of logic circuit sections, less in number than the scanning lines, for responding to combinations of the input numeral signal and its inverted replica, and an output distributing unit for assigning an output from one logic circuit section to at least two scanning lines. It is, therefore, possible to suppress an increase in the number of connection lines and of the logic circuit sections involving a high definition of a display device and hence to manufacture a display device in a high yield.

摘要翻译： 显示装置包括显示面板，用于向显示面板的扫描线提供扫描信号的扫描电路部分和用于提供n位（n：2或更多正整数）输入数字信号的扫描控制电路部分和 输入数字信号的反转副本到扫描电路部分。 在显示装置中，扫描电路部分包括具有用于接收输入数字信号的位和输入数字信号的反相副本的位的输入连接线组的输入连接线组，多个逻辑电路部分 用于响应输入数字信号和其反相副本的组合，以及输出分配单元，用于将来自一个逻辑电路部分的输出分配给至少两条扫描线。 因此，可以抑制连接线的数量的增加和涉及显示装置的高清晰度的逻辑电路部分的增加，从而以高产量制造显示装置。

公开(公告)号：US5801672A

公开(公告)日：1998-09-01

申请号：US432165

申请日：1995-05-08

申请人： Youichi Masuda ,  Nozomu Harada ,  Hiroki Nakamura

发明人： Youichi Masuda ,  Nozomu Harada ,  Hiroki Nakamura

IPC分类号： G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2310/021 ,  G09G2310/0224 ,  G09G2310/0232 ,  G09G2310/0283 ,  G09G2330/021 ,  G09G2330/08 ,  G09G2340/0407 ,  G09G2340/0471 ,  G09G2340/0478 ,  G09G2340/0485 ,  G09G3/2011

摘要： A display device comprises a display panel, a scanning circuit section for supplying a scanning signal to scanning lines of the display panel, and a scanning control circuit section for supplying an n-bit (n: 2 or more positive integer) input numeral signal and an inverted replica of the input numeral signal to the scanning circuit section. In the display device, a scanning circuit section comprises an input connection line group having sets of input connection lines for receiving bits of the input numeral signal and bits of the inverted replica of the input numeral signal, a plurality of logic circuit sections, less in number than the scanning lines, for responding to combinations of the input numeral signal and its inverted replica, and an output distributing unit for assigning an output from one logic circuit section to at least two scanning lines. It is, therefore, possible to suppress an increase in the number of connection lines and of the logic circuit sections involving a high definition of a display device and hence to manufacture a display device in a high yield.

摘要翻译： PCT No.PCT / JP94 / 01502 Sec。 371日期1995年5月8日 102（e）日期1995年5月8日PCT 1994年9月9日PCT公布。 WO95 / 07493 PCT出版物 日期1995年3月16日显示装置包括显示面板，用于向显示面板的扫描线提供扫描信号的扫描电路部分和用于提供n位（n：2或更多正整数）的扫描控制电路部分 ）输入数字信号和输入数字信号的反相副本到扫描电路部分。 在显示装置中，扫描电路部分包括具有用于接收输入数字信号的位和输入数字信号的反相副本的位的输入连接线组的输入连接线组，多个逻辑电路部分 用于响应输入数字信号和其反相副本的组合，以及输出分配单元，用于将来自一个逻辑电路部分的输出分配给至少两条扫描线。 因此，可以抑制连接线的数量的增加和涉及显示装置的高清晰度的逻辑电路部分的增加，从而以高产量制造显示装置。

公开(公告)号：US08610202B2

公开(公告)日：2013-12-17

申请号：US12894923

申请日：2010-09-30

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/1203 ,  H01L21/823885 ,  H01L21/84 ,  H01L29/78642

摘要： There is provided a semiconductor device which has a CMOS inverter circuit and which can accomplish high-integration by configuring an inverter circuit with a columnar structural body. A semiconductor device includes a columnar structural body which is arranged on a substrate and which comprises a p-type silicon, an n-type silicon, and an oxide arranged between the p-type silicon and the n-type silicon and running in the vertical direction to the substrate, n-type high-concentration silicon layers arranged on and below the p-type silicon, p-type high-concentration silicon layers arrange on and below the n-type silicon, an insulator which surrounds the p-type silicon, the n-type silicon, and the oxide, and which serves as a gate insulator, and a conductive body which surrounds the insulator and which serves as a gate electrode.

摘要翻译： 提供了具有CMOS反相器电路的半导体器件，其可以通过配置具有柱状结构体的逆变器电路来实现高集成度。 半导体器件包括柱状结构体，其被布置在衬底上，并且包括p型硅，n型硅和布置在p型硅和n型硅之间并在垂直方向上运行的氧化物 朝向衬底的方向，配置在p型硅和p型硅以上的n型高浓度硅层，p型高浓度硅层布置在n型硅的上方和下方，围绕p型硅的绝缘体 ，n型硅和氧化物，并且其用作栅极绝缘体，以及包围绝缘体并用作栅电极的导电体。

公开(公告)号：US08513717B2

公开(公告)日：2013-08-20

申请号：US13328574

申请日：2011-12-16

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/76 ,  H01L31/062 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823885 ,  H01L21/823487 ,  H01L27/0207 ,  H01L27/1104

摘要： A first driver transistor includes a first gate insulating film that surrounds a periphery of a first island-shaped semiconductor, a first gate electrode having a first surface that is in contact with the first gate insulating film, and first and second first-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first island-shaped semiconductor, respectively. A first load transistor includes a second gate insulating film having a first surface that is in contact with a second surface of the first gate electrode, a first arcuate semiconductor formed so as to be in contact with a portion of a second surface of the second gate insulating film, and first and second second-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first arcuate semiconductor, respectively. A first gate line extends from the first gate electrode and is made of the same material as the first gate electrode.

摘要翻译： 第一驱动器晶体管包括围绕第一岛状半导体的周边的第一栅极绝缘膜，具有与第一栅极绝缘膜接触的第一表面的第一栅极电极和第一和第二第一导电型 分别设置在第一岛状半导体的顶部和底部的高浓度半导体。 第一负载晶体管包括具有与第一栅电极的第二表面接触的第一表面的第二栅极绝缘膜，形成为与第二栅极的第二表面的一部分接触的第一弧形半导体 绝缘膜以及设置在第一弧形半导体的顶部和底部的第一和第二第二导电型高浓度半导体。 第一栅极线从第一栅电极延伸并且由与第一栅电极相同的材料制成。

公开(公告)号：US08471327B2

公开(公告)日：2013-06-25

申请号：US13163319

申请日：2011-06-17

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/788

CPC分类号： H01L29/7889 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825

摘要： A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the silicon substrate side, a floating gate arranged so as to surround the outer periphery of the channel region with a tunnel insulating film interposed between the floating gate and the channel region, a control gate arranged so as to surround the outer periphery of the floating gate with an inter-polysilicon insulating film interposed between the control gate and the floating gate, and a control gate line electrically connected to the control gate and extending in a predetermined direction. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the lower and inner side surfaces of the control gate and between the floating gate and the lower surface of the control gate line.

公开(公告)号：US20120264265A1

公开(公告)日：2012-10-18

申请号：US13534615

申请日：2012-06-27

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L21/336

CPC分类号： H01L27/092 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78642

摘要： It is an object to allow an inverter to be made up using a single island-shaped semiconductor, so as to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit. The object is achieved by a semiconductor device which comprises an island-shaped semiconductor layer, a first gate dielectric film surrounding a periphery of the island-shaped semiconductor layer, a gate electrode surrounding a periphery of the first gate dielectric film, a second gate dielectric film surrounding a periphery of the gate electrode, a tubular semiconductor layer surrounding a periphery of the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer disposed on top of the island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer disposed underneath the island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer disposed on top of the tubular semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer disposed underneath the tubular semiconductor layer.

摘要翻译： 本发明的目的是允许使用单个岛状半导体构成逆变器，以提供包括高度集成的基于SGT的CMOS反相器电路的半导体器件。 该目的通过一种半导体器件实现，该半导体器件包括岛状半导体层，围绕岛状半导体层的周围的第一栅极电介质膜，围绕第一栅极电介质膜周围的栅电极，第二栅极电介质 围绕所述栅电极的周围的薄膜，围绕所述第二栅极电介质膜的周围的管状半导体层，设置在所述岛状半导体层的顶部的第一第一导电型高浓度半导体层， 布置在岛状半导体层下方的导电型高浓度半导体层，设置在管状半导体层顶部的第一第二导电型高浓度半导体层和第二第二导电型高浓度半导体层 层设置在管状半导体层下方。

公开(公告)号：US20120135271A1

公开(公告)日：2012-05-31

申请号：US13322638

申请日：2010-05-27

申请人： Toshihiko Ooi ,  Hiroki Nakamura ,  Shinji Ootsuka ,  Hiroyuki Masuoka ,  Masahiro Yoshida

发明人： Toshihiko Ooi ,  Hiroki Nakamura ,  Shinji Ootsuka ,  Hiroyuki Masuoka ,  Masahiro Yoshida

IPC分类号： B32B15/01

CPC分类号： C23C2/12 ,  B32B15/012 ,  B32B15/013 ,  C22C18/04 ,  C22C21/10 ,  C23C2/06 ,  Y10T428/12757 ,  Y10T428/12799

摘要： A hot dip Al—Zn coated steel sheet exhibits excellent corrosion resistance. The Al content in a coated film is 20-95% by mass. The Ca content is 0.01-10% by mass. Alternatively, the total content of Ca and Mg is 0.01-10% by mass. Preferably, the coated film includes an upper layer and an alloy phase present at the interface to a substrate steel sheet, and Ca or Ca and Mg are contained primarily in the upper layer. Also preferably, the Ca or Ca and Mg include an intermetallic compound with at least one type selected from Zn, Al, and Si. If Ca or Ca and Mg are contained in the coated film, as described above, these elements are contained in corrosion products generated in a bonded portion and exert effects of stabilizing the corrosion products and retarding proceeding of corrosion thereafter. Then, as a result, the corrosion resistance is improved.

摘要翻译： 热浸镀铝锌钢板表现出优异的耐腐蚀性。 涂膜中的Al含量为20〜95质量％。 Ca含量为0.01〜10质量％。 或者，Ca和Mg的总含量为0.01〜10质量％。 优选地，涂膜包括在与基板钢板的界面处存在的上层和合金相，并且Ca或Ca和Mg主要包含在上层中。 还优选地，Ca或Ca和Mg包括具有选自Zn，Al和Si中的至少一种的金属间化合物。 如果如上所述，如果在涂膜中含有Ca或Ca和Mg，则这些元素被包含在接合部分产生的腐蚀产物中，并且具有稳定腐蚀产物的作用，并且此后延迟腐蚀进行。 结果，耐腐蚀性提高。

公开(公告)号：US08178399B1

公开(公告)日：2012-05-15

申请号：US13354579

申请日：2012-01-20

申请人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66666

摘要： An SGT production method includes forming a pillar-shaped first-conductive-type semiconductor layer and forming a second-conductive-type semiconductor layer underneath the first-conductive-type semiconductor layer. A dummy gate dielectric film and a dummy gate electrode are formed around the first-conductive-type semiconductor layer and a first dielectric film is formed on an upper region of a sidewall of the first-conductive-type semiconductor layer in contact with a top of the gate electrode. A first dielectric film is formed on a sidewall of the gate electrode and a second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer. A second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer and a metal-semiconductor compound is formed on each of the second-conductive-type semiconductor layers. The dummy gate dielectric film and the dummy gate electrode are removed and a high-k gate dielectric film and a metal gate electrode are formed.

摘要翻译： SGT制造方法包括形成柱状的第一导电型半导体层，在第一导电型半导体层的下方形成第二导电型半导体层。 在第一导电型半导体层周围形成虚拟栅极电介质膜和虚拟栅电极，并且第一电介质膜形成在第一导电型半导体层的与顶部接触的第一导电型半导体层的侧壁的上部区域 栅电极。 第一电介质膜形成在栅电极的侧壁上，第二导电型半导体层形成在第一导电型半导体层的上部。 第二导电型半导体层形成在第一导电型半导体层的上部，并且在每个第二导电型半导体层上形成金属半导体化合物。 除去虚拟栅极电介质膜和虚拟栅电极，形成高k栅极电介质膜和金属栅电极。

公开(公告)号：US20120025291A1

公开(公告)日：2012-02-02

申请号：US13163319

申请日：2011-06-17

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7889 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825

摘要： A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the silicon substrate side, a floating gate arranged so as to surround the outer periphery of the channel region with a tunnel insulating film interposed between the floating gate and the channel region, a control gate arranged so as to surround the outer periphery of the floating gate with an inter-polysilicon insulating film interposed between the control gate and the floating gate, and a control gate line electrically connected to the control gate and extending in a predetermined direction. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the lower and inner side surfaces of the control gate and between the floating gate and the lower surface of the control gate line.

摘要翻译： 非易失性半导体存储晶体管包括岛状半导体，其具有从硅衬底侧依次形成的源极区，沟道区和漏极区，浮置栅极，以围绕沟道区的外周的方式布置， 插入在所述浮置栅极和所述沟道区域之间的隧道绝缘膜，控制栅极，其布置成围绕所述浮置栅极的外周，所述控制栅极具有介于所述控制栅极和所述浮置栅极之间的多晶硅间绝缘膜，以及控制栅极 线路电连接到控制门并沿预定方向延伸。 多晶硅间绝缘膜被布置成插入在控制栅极的浮动栅极和下侧和内侧表面之间以及浮动栅极和控制栅极线的下表面之间。