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1.发明授权Sensor network system for acquiring high quality speech signals and communication method therefor 失效用于获取高质量语音信号的传感器网络系统及其通信方法公开(公告)号：US08600443B2
公开(公告)日：2013-12-03
申请号：US13547426
申请日：2012-07-12
IPC分类号： H04B1/38
CPC分类号： H04R3/005 , G10L2021/02166 , H04R1/406 , H04R2201/401
摘要： A sensor network system including node devices connected in a network via predetermined propagation paths collects data measured at each node device to be aggregated into one base station via a time-synchronized sensor network system. The base station calculates a position of the signal source based on the angle estimation value of the signal from each node device and position information thereof, designates a node device located nearest to the signal source as a cluster head node device, and transmits information of the position of the signal source and the designated cluster head node device to each node device, to cluster each node device located within the number of hops from the cluster head node device as a node device belonging to each cluster. Each node device performs an emphasizing process on the received signal from the signal source, and transmits an emphasized signal to the base station.
摘要翻译： 包括经由预定传播路径连接在网络中的节点设备的传感器网络系统经由时间同步的传感器网络系统收集在每个节点设备测量的要聚合成一个基站的数据。 基站基于来自各节点装置的信号的角度估计值及其位置信息来计算信号源的位置，将位于最靠近信号源的节点装置指定为簇头节点装置，并发送信息源 信号源和指定的簇头节点设备的位置到每个节点设备，将位于簇头节点设备内的跳数内的每个节点设备聚类为属于每个集群的节点设备。 每个节点设备对来自信号源的接收信号执行强调处理，并将强调信号发送到基站。
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2.发明授权Ad converter and TD converter configured without operational amplifier and capacitor 失效Ad转换器和TD转换器配置无运算放大器和电容公开(公告)号：US08519880B2
公开(公告)日：2013-08-27
申请号：US13470605
申请日：2012-05-14
IPC分类号： H03M1/50
摘要： An AD converter includes a VT converter circuit part which inputs an analog input voltage and a sampling clock, converts the analog input voltage to a corresponding delay time, and outputs time domain data. A ring oscillator circuit part of N stages inputs the time domain data, and an error propagation circuit part takes out delay information containing a quantization error from phase information of the ring oscillator circuit part of the previous stage, and propagate the delay information to the ring oscillator circuit part of a subsequent stage. A counter circuit part measures a number of waves of an output oscillation waveform of the ring oscillator circuit part of each stage, and an output signal generator part generates an output signal from an output counted value of each counter circuit part. A reset part resets each error propagation circuit part and each counter circuit part with a sampling clock.
摘要翻译： AD转换器包括输入模拟输入电压和采样时钟的VT转换器电路部分，将模拟输入电压转换为相应的延迟时间，并输出时域数据。 N级的环形振荡器电路部分输入时域数据，误差传播电路部分从前级的环形振荡电路部分的相位信息中取出包含量化误差的延迟信息，并将延迟信息传播到环 振荡电路是后续阶段的一部分。 计数器电路部分测量每个级的环形振荡器电路部分的输出振荡波形的波数，并且输出信号发生器部分根据每个计数器电路部分的输出计数值产生输出信号。 复位部分将采样时钟复位每个误差传播电路部分和每个计数器电路部分。
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3.发明申请SENSOR NETWORK SYSTEM FOR ACUIRING HIGH QUALITY SPEECH SIGNALS AND COMMUNICATION METHOD THEREFOR 失效用于获取高质量语音信号的传感器网络系统及其通信方法公开(公告)号：US20130029684A1
公开(公告)日：2013-01-31
申请号：US13547426
申请日：2012-07-12
IPC分类号： H04W24/00
CPC分类号： H04R3/005 , G10L2021/02166 , H04R1/406 , H04R2201/401
摘要： A sensor network system including node devices connected in a network via predetermined propagation paths collects data measured at each node device to be aggregated into one base station via a time-synchronized sensor network system. The base station calculates a position of the signal source based on the angle estimation value of the signal from each node device and position information thereof, designates a node device located nearest to the signal source as a cluster head node device, and transmits information of the position of the signal source and the designated cluster head node device to each node device, to cluster each node device located within the number of hops from the cluster head node device as a node device belonging to each cluster. Each node device performs an emphasizing process on the received signal from the signal source, and transmits an emphasized signal to the base station.
摘要翻译： 包括经由预定传播路径连接在网络中的节点设备的传感器网络系统经由时间同步的传感器网络系统收集在每个节点设备测量的要聚合成一个基站的数据。 基站基于来自各节点装置的信号的角度估计值及其位置信息来计算信号源的位置，将位于最靠近信号源的节点装置指定为簇头节点装置，并发送信息源 信号源和指定的簇头节点设备的位置到每个节点设备，将位于簇头节点设备内的跳数内的每个节点设备聚类为属于每个集群的节点设备。 每个节点设备对来自信号源的接收信号执行强调处理，并将强调信号发送到基站。
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4.发明申请AD CONVERTER AND TD CONVERTER CONFIGURED WITHOUT OPERATIONAL AMPLIFIER AND CAPACITOR 失效AD转换器和TD转换器配置无运算放大器和电容器公开(公告)号：US20120286987A1
公开(公告)日：2012-11-15
申请号：US13470605
申请日：2012-05-14
IPC分类号： H03M1/50
摘要： An AD converter includes a VT converter circuit part which inputs an analog input voltage and a sampling clock, converts the analog input voltage to a corresponding delay time, and outputs time domain data. A ring oscillator circuit part of N stages inputs the time domain data, and an error propagation circuit part takes out delay information containing a quantization error from phase information of the ring oscillator circuit part of the previous stage, and propagate the delay information to the ring oscillator circuit part of a subsequent stage. A counter circuit part measures a number of waves of an output oscillation waveform of the ring oscillator circuit part of each stage, and an output signal generator part generates an output signal from an output counted value of each counter circuit part. A reset part resets each error propagation circuit part and each counter circuit part with a sampling clock.
摘要翻译： AD转换器包括输入模拟输入电压和采样时钟的VT转换器电路部分，将模拟输入电压转换为相应的延迟时间，并输出时域数据。 N级的环形振荡器电路部分输入时域数据，误差传播电路部分从前级的环形振荡电路部分的相位信息中取出包含量化误差的延迟信息，并将延迟信息传播到环 振荡电路是后续阶段的一部分。 计数器电路部分测量每个级的环形振荡器电路部分的输出振荡波形的波数，并且输出信号发生器部分根据每个计数器电路部分的输出计数值产生输出信号。 复位部分将采样时钟复位每个误差传播电路部分和每个计数器电路部分。
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公开(公告)号：US20130223137A1
公开(公告)日：2013-08-29
申请号：US13816718
申请日：2011-08-14
IPC分类号： G11C11/417
CPC分类号： G11C11/417 , G11C8/12 , G11C8/14 , G11C11/412 , G11C11/413 , G11C15/00 , G11C15/04 , G11C29/74 , G11C2211/5641
摘要： Provided is memory which is capable of dynamically changing memory cell bit reliability and of switching the operating mode so as to accommodate process variations, thereby reducing the operating voltage. The memory is provided with a mode control line selection circuit for dividing mode control lines in to word units and using control line selection signals and global control signals to control the mode control lines divided into word units, and a word line selection circuit for dividing the word lines that control the conduction of switching unit into word units and using word line selection signals and global word signals to control the word lines divided into word units. The mode control line switching circuit is used to switch between a 1 bit/1 cell mode and a 1 bit/n cell mode in word units.
摘要翻译： 提供了能够动态地改变存储单元位可靠性和切换操作模式以适应过程变化的存储器，从而降低工作电压。 存储器设置有模式控制线选择电路，用于将模式控制线分成单位，并且使用控制线选择信号和全局控制信号来控制分成字单元的模式控制线，以及字线选择电路，用于将 控制开关单元导通到单元的字线，并使用字线选择信号和全局字信号来控制划分为字单位的字线。 模式控制线切换电路用于以单位单位在1位/ 1个单元模式和1位/ n单元模式之间切换。
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公开(公告)号：US08787075B2
公开(公告)日：2014-07-22
申请号：US13816718
申请日：2011-08-14
IPC分类号： G11C11/00 , G11C11/412 , G11C11/417 , G11C8/12 , G11C15/04 , G11C11/413 , G11C8/14 , G11C15/00
CPC分类号： G11C11/417 , G11C8/12 , G11C8/14 , G11C11/412 , G11C11/413 , G11C15/00 , G11C15/04 , G11C29/74 , G11C2211/5641
摘要： Provided is memory which is capable of dynamically changing memory cell bit reliability and of switching the operating mode so as to accommodate process variations, thereby reducing the operating voltage. The memory is provided with a mode control line selection circuit for dividing mode control lines in to word units and using control line selection signals and global control signals to control the mode control lines divided into word units, and a word line selection circuit for dividing the word lines that control the conduction of switching unit into word units and using word line selection signals and global word signals to control the word lines divided into word units. The mode control line switching circuit is used to switch between a 1 bit/1 cell mode and a 1 bit/n cell mode in word units.
摘要翻译： 提供了能够动态地改变存储单元位可靠性和切换操作模式以适应过程变化的存储器，从而降低工作电压。 存储器设置有模式控制线选择电路，用于将模式控制线分成单位，并且使用控制线选择信号和全局控制信号来控制分成字单元的模式控制线，以及字线选择电路，用于将 控制开关单元导通到单元的字线，并使用字线选择信号和全局字信号来控制划分为字单位的字线。 模式控制线切换电路用于以单位单位在1位/ 1个单元模式和1位/ n单元模式之间切换。
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公开(公告)号：US08238140B2
公开(公告)日：2012-08-07
申请号：US12809684
申请日：2009-01-07
CPC分类号： G11C11/4125 , G11C5/005
摘要： A memory wherein the bit reliability of the memory cells can be dynamically varied depending on the application or the memory status, the operation stability is ensured, and thereby a low power consumption and a high reliability are realized. Either a mode (a 1-bit/1-cell mode) in which one bit is composed of one memory cell or a mode (a 1-bit/n-cell mode) in which one bit is composed of n (n is two or more) connected memory cells is dynamically selected. When the 1-bit/n-cell mode is selected, the read/write stability of one bit is enhanced, the cell current during read is increased (read is speeded up), and a bit error, if occurs, is self-corrected. Especially, a pair of CMOS transistors and a control line for performing control so as to permit the CMOS transistors to conduct are added between the data holding nodes of n adjacent memory cells. With this, the word line (WL) is controlled, and thereby the operation stability is further improved.
摘要翻译： 可以根据应用或存储器状态来动态地改变存储器单元的位可靠性的存储器，从而确保操作稳定性，从而实现低功耗和高可靠性。 一个位由一个存储器单元组成的模式（1位/ 1单元模式）或其中一个位由n组成的模式（1位/ n单元模式） 或更多）连接的存储器单元被动态地选择。 当选择1位/ n单元模式时，增加了一位的读/写稳定性，读取期间的单元电流增加（读取速度加快），如果出现位错误，则自校正 。 特别地，在n个相邻的存储单元的数据保持节点之间添加一对CMOS晶体管和用于执行控制以允许CMOS晶体管导通的控制线。 由此，对字线（WL）进行控制，从而进一步提高操作稳定性。
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8.发明申请CIRCUIT STARTUP METHOD AND CIRCUIT STARTUP APPARATUS UTILIZING UTTERANCE ESTIMATION FOR USE IN SPEECH PROCESSING SYSTEM PROVIDED WITH SOUND COLLECTING DEVICE 审中-公开电路启动方法和电路启动装置使用用于使用声音收集装置提供的语音处理系统中的使用估计公开(公告)号：US20100292987A1
公开(公告)日：2010-11-18
申请号：US12774923
申请日：2010-05-06
IPC分类号： G10L15/20
摘要： A circuit startup method utilizing utterance estimation in a speech processing system including a sound collecting device is provided. The circuit startup method includes a subset power supply step of supplying power to the sound collecting device and a signal processing circuit, and a sound collecting step of inputting a sound from the sound collecting device through the signal processing circuit. The circuit startup method further includes an utterance estimation step of estimating whether or not a speech is contained in the inputted sound, and a power supply step of supplying power to the speech processing circuit for an utterance interval when it is estimated that a speech is contained from an estimation result of the utterance estimation step.
摘要翻译： 提供一种在包括声音采集装置的语音处理系统中利用话语估计的电路启动方法。 电路启动方法包括向收音装置供电的子集电源步骤和信号处理电路，以及通过信号处理电路从声音采集装置输入声音的声音采集步骤。 电路启动方法还包括：估计语音是否包含在输入声音中的话语估计步骤;以及当估计出包含语音时，向语音处理电路供给话音间隔的电力供给步骤 根据话语估计步骤的估计结果。
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9.发明授权Program controlling method having transfer of code and data among programs and apparatus therefor 失效程序控制方法，其程序和装置之间具有代码和数据的传送
公开(公告)号：US5894573A
公开(公告)日：1999-04-13
申请号：US812080
申请日：1997-03-06
CPC分类号： G06F9/44521 , G06F9/44552
摘要： An arrangement for executing a process in a data processing system using first and second programs each including executable codes and data in coordinated fashion in which a portion of the data and executable codes from the first program is provided to the second program during execution of the process. In execution of the process, portions of the data and executable codes provided by the first program to the second program are forcibly added or forcibly substituted and executed by the second program. The data and executable code portions are provided by injection and the injection and execution are conducted by imparting an acknowledgement of the addition or substitution and execution to the first program by the second program.
摘要翻译： 一种用于在数据处理系统中执行处理的装置，其使用第一和第二程序，每个程序包括协调方式的可执行代码和数据，其中来自第一程序的数据和可执行代码的一部分在执行过程期间被提供给第二程序 。 在执行该处理时，由第一程序提供给第二程序的数据和可执行代码的部分被第二程序强制地增加或被强制替代和执行。 通过注入提供数据和可执行代码部分，并且通过由第二程序向第一程序赋予加法或替换和执行的确认来执行注入和执行。
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10.发明授权Serial access memory device capable of controlling order of access to memory cell areas 失效能够控制访问存储单元区域的顺序的串行存取存储器件
公开(公告)号：US5633829A
公开(公告)日：1997-05-27
申请号：US739786
申请日：1991-07-31
摘要： A serial access memory device is disclosed in which order of access to writing and reading memory cell columns can be controlled. A writing column selecting circuit and a reading column selecting circuit are each comprised of ring pointers with a controllable number of stages. The number of stages of the ring pointers is controlled in response to control signals stored in a serial interface circuit. As a result, two ring pointers each having two stages are formed in the writing column selecting circuit while one ring pointer having four stages is formed in the reading column selecting circuit. After two data signals are written in selected two memory cell columns in parallel, written data signals are read out from serially selected four memory cell columns at a speed twice that in the writing. This serial access memory device is applied to a progressive scan conversion circuit for video signal processing.
摘要翻译： 公开了可以控制对写入和读取存储单元列的存取顺序的串行存取存储器件。 写入列选择电路和读取列选择电路各自包括具有可控级数的环形指针。 响应于存储在串行接口电路中的控制信号来控制环形指针的级数。 结果，在写入列选择电路中形成两个具有两级的环形指针，同时在读取列选择电路中形成具有四级的一个环形指针。 在两个数据信号并行写入所选择的两个存储单元列之后，以写入的两倍的速度从串行选择的四个存储单元列中读出写入的数据信号。 该串行访问存储器件被应用于用于视频信号处理的逐行扫描转换电路。
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