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    Semiconductor memory and program
    1.
    发明授权
    Semiconductor memory and program 有权
    半导体存储器和程序

    公开(公告)号：US08238140B2

    公开(公告)日：2012-08-07

    申请号：US12809684

    申请日：2009-01-07

    申请人： Masahiko Yoshimoto ,  Hiroshi Kawaguchi ,  Shunsuke Okumura ,  Hidehiro Fujiwara

    发明人： Masahiko Yoshimoto ,  Hiroshi Kawaguchi ,  Shunsuke Okumura ,  Hidehiro Fujiwara

    IPC分类号： G11C11/24 ,  G11C11/00 ,  G11C7/00 ,  G11C7/02 ,  G11C29/00

    CPC分类号： G11C11/4125 ,  G11C5/005

    摘要： A memory wherein the bit reliability of the memory cells can be dynamically varied depending on the application or the memory status, the operation stability is ensured, and thereby a low power consumption and a high reliability are realized. Either a mode (a 1-bit/1-cell mode) in which one bit is composed of one memory cell or a mode (a 1-bit/n-cell mode) in which one bit is composed of n (n is two or more) connected memory cells is dynamically selected. When the 1-bit/n-cell mode is selected, the read/write stability of one bit is enhanced, the cell current during read is increased (read is speeded up), and a bit error, if occurs, is self-corrected. Especially, a pair of CMOS transistors and a control line for performing control so as to permit the CMOS transistors to conduct are added between the data holding nodes of n adjacent memory cells. With this, the word line (WL) is controlled, and thereby the operation stability is further improved.

    摘要翻译： 可以根据应用或存储器状态来动态地改变存储器单元的位可靠性的存储器，从而确保操作稳定性，从而实现低功耗和高可靠性。 一个位由一个存储器单元组成的模式（1位/ 1单元模式）或其中一个位由n组成的模式（1位/ n单元模式） 或更多）连接的存储器单元被动态地选择。 当选择1位/ n单元模式时，增加了一位的读/写稳定性，读取期间的单元电流增加（读取速度加快），如果出现位错误，则自校正 。 特别地，在n个相邻的存储单元的数据保持节点之间添加一对CMOS晶体管和用于执行控制以允许CMOS晶体管导通的控制线。 由此，对字线（WL）进行控制，从而进一步提高操作稳定性。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08659969B2

    公开(公告)日：2014-02-25

    申请号：US13215217

    申请日：2011-08-22

    申请人： Hidehiro Fujiwara ,  Koji Nii ,  Makoto Yabuuchi ,  Kazutami Arimoto

    发明人： Hidehiro Fujiwara ,  Koji Nii ,  Makoto Yabuuchi ,  Kazutami Arimoto

    IPC分类号： G11C5/14

    CPC分类号： G11C16/20 ,  G11C7/24 ,  G11C29/44

    摘要： By using a fact that a bit error in an on-chip embedded memory occurs at a random address, means for creating a chip-unique ID and utilizing this ID are provided. A controller having received a verification request from outside instructs a variable power supply circuit to decrease a voltage supplied to a memory to be lower than that at the normal operation time. When the voltage supplied to the memory is stabilized, the controller requests a memory test to a memory BIST. By using an address where an error occurs due to a result of the memory test, the controller creates the chip-unique ID and uses the ID as a response to the verification request.

    摘要翻译： 通过使用片上嵌入式存储器中的位错误发生在随机地址处的事实，提供了用于创建芯片唯一ID并利用该ID的装置。 已经从外部接收到验证请求的控制器指示可变电源电路将提供给存储器的电压降低到低于正常操作时间的电压。 当提供给存储器的电压稳定时，控制器向存储器BIST请求存储器测试。 通过使用由于存储器测试的结果而出现错误的地址，控制器创建芯片唯一ID，并使用ID作为对验证请求的响应。

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120044777A1

    公开(公告)日：2012-02-23

    申请号：US13215217

    申请日：2011-08-22

    申请人： Hidehiro FUJIWARA ,  Koji NII ,  Makoto Yabuuchi ,  Kazutami Arimoto

    发明人： Hidehiro FUJIWARA ,  Koji NII ,  Makoto Yabuuchi ,  Kazutami Arimoto

    IPC分类号： G11C7/00

    CPC分类号： G11C16/20 ,  G11C7/24 ,  G11C29/44

    摘要： By using a fact that a bit error in an on-chip embedded memory occurs at a random address, means for creating a chip-unique ID and utilizing this ID are provided. A controller having received a verification request from outside instructs a variable power supply circuit to decrease a voltage supplied to a memory to be lower than that at the normal operation time. When the voltage supplied to the memory is stabilized, the controller requests a memory test to a memory BIST. By using an address where an error occurs due to a result of the memory test, the controller creates the chip-unique ID and uses the ID as a response to the verification request.

    摘要翻译： 通过使用片上嵌入式存储器中的位错误发生在随机地址处的事实，提供了用于创建芯片唯一ID并利用该ID的装置。 已经从外部接收到验证请求的控制器指示可变电源电路将提供给存储器的电压降低到低于正常操作时间的电压。 当提供给存储器的电压稳定时，控制器向存储器BIST请求存储器测试。 通过使用由于存储器测试的结果而出现错误的地址，控制器创建芯片唯一ID，并使用ID作为对验证请求的响应。