利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

30 条记录 (耗时 0.025 秒)

    Semiconductor memory device permitting high speed data transfer and high density integration
    1.
    发明授权
    Semiconductor memory device permitting high speed data transfer and high density integration 失效
    半导体存储器件允许高速数据传输和高密度集成

    公开(公告)号：US5586076A

    公开(公告)日：1996-12-17

    申请号：US304899

    申请日：1994-09-13

    申请人： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Kiyohiro Furutani ,  Shigeru Kikuda

    发明人： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Kiyohiro Furutani ,  Shigeru Kikuda

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00 ,  G11C11/24

    CPC分类号： G11C11/4096 ,  G11C7/10

    摘要： In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.

    摘要翻译： 在存储单元阵列中，数据线被形成为每个块提供的子数据线和每个块共同的主数据线的分层布置，以及由属于块的子数据线之间的列地址选择的子数据线 通过行地址同时选择连接到位线。 因此，减少了子数据线的长度，这降低了浮动电容，可以高速地执行读和写操作，并且可以选择性地操作子数据线。 此外，可以减少对子数据线进行充电所需的功率，并且可以减小半导体存储器件的整体功耗。

    Redundancy circuit for repairing defective bits in semiconductor memory device
    2.
    发明授权
    Redundancy circuit for repairing defective bits in semiconductor memory device 失效
    用于修复半导体存储器件中的有缺陷的位的冗余电路

    公开(公告)号：US5574729A

    公开(公告)日：1996-11-12

    申请号：US338817

    申请日：1994-11-10

    申请人： Mitsuya Kinoshita ,  Shigeru Mori ,  Yoshikazu Morooka ,  Hiroshi Miyamoto ,  Shigeru Kikuda ,  Makoto Suwa

    发明人： Mitsuya Kinoshita ,  Shigeru Mori ,  Yoshikazu Morooka ,  Hiroshi Miyamoto ,  Shigeru Kikuda ,  Makoto Suwa

    IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/00

    CPC分类号： G11C29/848

    摘要： A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.

    摘要翻译： 一种半导体存储器件包括多个存储块，i个在多个存储块上延伸的主行或列选择线，以及用于根据所施加的地址信号选择主行或列选择线中的一个的解码器。 解码器包括i个输出。 每个存储块包括排列成行和列的多个存储器单元和至少（i + 1）个子行或列选择线，每个用于选择一行或一列存储单元。 为每个存储块提供移位冗余电路，用于连接主行或列选择线和子行或列选择线。 移位冗余电路包括用于将一个主行或列选择线连接到多个相邻子行或列选择线中的一个的开关电路和用于设置开关电路的连接路径的电路。 除了与有缺陷的位相关联的有缺陷的子行或列选择线之外，移位冗余电路将连续相邻的子行或列选择线以一对一的对应方式连接到主行或列选择线。

    Semiconductor device having no through current flow in standby period
    3.
    发明授权
    Semiconductor device having no through current flow in standby period 失效
    半导体器件在待机期间没有通过电流流动

    公开(公告)号：US5321654A

    公开(公告)日：1994-06-14

    申请号：US863975

    申请日：1992-04-06

    申请人： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Mori ,  Shigeru Kikuda ,  Makoto Suwa ,  Mitsuya Kinoshita

    发明人： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Mori ,  Shigeru Kikuda ,  Makoto Suwa ,  Mitsuya Kinoshita

    IPC分类号： G11C11/408 ,  G11C5/14 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401 ,  G11C11/409 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  G11C7/00

    CPC分类号： G11C7/22 ,  G11C5/14 ,  G11C8/18

    摘要： A semiconductor device having amplifying circuits provided near corresponding bonding pads receiving external signals, and positioned between the bonding pads and internal circuits to which such external signals are to be applied. The device includes a control signal generating circuit for the amplifying circuits which is not provided in conventional semiconductor devices. In response to external control signals, the control signal generating circuit generates internal control signals for controlling electric paths between a power supply and ground in the amplifying circuits. During the standby period of the semiconductor device, the paths between the power supply and ground are cut regardless of the potential of the corresponding bonding pads, preventing flow of a through current.

    摘要翻译： 一种具有放大电路的半导体器件，该放大电路设置在相应的接合焊盘附近，接收外部信号，并且位于接合焊盘和要施加这样的外部信号的内部电路之间。 该装置包括用于放大电路的控制信号发生电路，其不在常规半导体器件中提供。 响应于外部控制信号，控制信号发生电路产生用于控制放大电路中的电源和接地之间的电气路径的内部控制信号。 在半导体器件的待机期间，电源和接地之间的路径被切断，而不管相应的焊盘的电位如何，防止通过电流的流动。

    Semiconductor memory device comprising a test circuit and a method of operation thereof
    6.
    发明授权
    Semiconductor memory device comprising a test circuit and a method of operation thereof 失效
    半导体存储器件，包括测试电路及其操作方法

    公开(公告)号：US5384784A

    公开(公告)日：1995-01-24

    申请号：US750040

    申请日：1991-08-27

    申请人： Shigeru Mori ,  Makoto Suwa ,  Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Kikuda ,  Mitsuya Kinoshita

    发明人： Shigeru Mori ,  Makoto Suwa ,  Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Kikuda ,  Mitsuya Kinoshita

    IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C29/00 ,  G11C29/34 ,  G06F15/20

    CPC分类号： G11C29/34

    摘要： A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.

    摘要翻译： 半导体存储器件包括存储器阵列。 存储器阵列中奇数次序的位线对属于第一组，偶数顺序的位线对属于第二组。 第一放大器连接到每个位线对。 对应于第一组，写总线读总线和读/测电路。 对应于第二组，写总线读总线和读/测电路。 列解码器在测试时同时选择多个位线对。 在测试时，每个读/测试电路将从属于相应组的多个位线对中读出的数据与给定的预期数据进行比较，以提供比较结果。

    Semiconductor memory device carrying out input and output of data in a predetermined bit organization
    8.
    发明授权
    Semiconductor memory device carrying out input and output of data in a predetermined bit organization 失效
    在预定位组织中执行数据的输入和输出的半导体存储器件

    公开(公告)号：US5537351A

    公开(公告)日：1996-07-16

    申请号：US301754

    申请日：1994-09-07

    申请人： Makoto Suwa ,  Yoshikazu Morooka ,  Kiyohiro Furutani

    发明人： Makoto Suwa ,  Yoshikazu Morooka ,  Kiyohiro Furutani

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C29/00 ,  G11C29/14 ,  G11C29/28 ,  G11C29/48 ,  G11C8/00

    CPC分类号： G11C29/48 ,  G11C29/28 ,  G11C7/1006

    摘要： In a general read out operation, data read out from a memory cell array is amplified by a preamplifier group. The amplified data is provided to a selector unit. The selector unit responds to a bit organization select signal to select data according to a predetermined bit configuration. The selected data is provided to a data bus. In a test mode, the selector unit responds to a test mode signal to provide a test result to a data bus corresponding to a predetermined bit organization. Therefore, only the required data bus is used according to the bit organization and the test mode.

    摘要翻译： 在一般的读出操作中，从存储单元阵列读出的数据由前置放大器组放大。 放大数据被提供给选择器单元。 选择器单元响应位组织选择信号以根据预定位配置选择数据。 所选择的数据被提供给数据总线。 在测试模式中，选择器单元响应于测试模式信号，以向与预定位组织相对应的数据总线提供测试结果。 因此，仅根据位组织和测试模式使用所需的数据总线。

    Semiconductor memory device having controllable supplying capability of internal voltage
    9.
    发明授权
    Semiconductor memory device having controllable supplying capability of internal voltage 失效
    具有可控的内部电压供应能力的半导体存储器件

    公开(公告)号：US5995435A

    公开(公告)日：1999-11-30

    申请号：US137707

    申请日：1998-08-21

    申请人： Takeshi Hamamoto ,  Kiyohiro Furutani ,  Yoshikazu Morooka

    发明人： Takeshi Hamamoto ,  Kiyohiro Furutani ,  Yoshikazu Morooka

    IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C13/00

    CPC分类号： G11C11/4085 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/146

    摘要： When an external RAS and external CAS are input to a RAS buffer and a CAS buffer, an internal RAS and an internal CAS are generated. The internal RAS is input to a clock generating circuit and a CBR mode determination circuit and the internal CAS is input to the CBR mode determination circuit. The clock generating circuit outputs a pump clock to first and second WL pumps upon input of internal RAS, and the first WL pump supplies charge to a Vpp power supply. If CAS is input prior to RAS during refresh operation, CBR mode determination circuit inputs a CBR mode signal to the second WL pump which supplies charge to Vpp power supply together with the first WL pump when the pump clock and the CBR mode signal is input thereto.

    摘要翻译： 当外部+ E，ovs RAS + EE和外部+ E，ovs CAS + EE输入到RAS缓冲区，CAS缓冲区，内部+ E，ovs RAS + EE和内部+ E，ovs CAS + EE 生成。 内部+ E，ovs RAS + EE输入到时钟发生电路和CBR模式确定电路，内部+ E，ovs CAS + EE输入到CBR模式确定电路。 时钟发生电路在内部+ E，RAS + EE输入时向第一和第二WL泵输出泵时钟，第一WL泵为Vpp电源供电。 如果+ E，则在+ E之前输入ovs CAS + EE，在刷新操作期间输入ovs RAS + EE，CBR模式确定电路将CBR模式信号输入到与第一WL泵一起向Vpp电源提供电荷的第二WL泵 当泵时钟和CBR模式信号被输入时。

    Semiconductor memory device having controllable supplying capability of internal voltage
    10.
    发明授权
    Semiconductor memory device having controllable supplying capability of internal voltage 失效
    具有可控的内部电压供应能力的半导体存储器件

    公开(公告)号：US5699303A

    公开(公告)日：1997-12-16

    申请号：US645347

    申请日：1996-05-13

    申请人： Takeshi Hamamoto ,  Kiyohiro Furutani ,  Yoshikazu Morooka

    发明人： Takeshi Hamamoto ,  Kiyohiro Furutani ,  Yoshikazu Morooka

    IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C13/00

    CPC分类号： G11C11/4085 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/146

    摘要： When an external RAS and external CAS are input to a RAS buffer and a CAS buffer, an internal RAS and an internal CAS are generated. The internal RAS is input to a clock generating circuit and a CBR mode determination circuit and the internal CAS is input to the CBR mode determination circuit. The clock generating circuit outputs a pump clock to first and second WL pumps upon input of internal RAS, and the first WL pump supplies charge to a Vpp power supply. If CAS is input prior to RAS during refresh operation, CBR mode determination circuit inputs a CBR mode signal to the second WL pump which supplies charge to Vpp power supply together with the first WL pump when the pump clock and the CBR mode signal is input thereto.

    摘要翻译： 当外部+ E，ovs RAS + EE和外部+ E，ovs CAS + EE输入到RAS缓冲区，CAS缓冲区，内部+ E，ovs RAS + EE和内部+ E，ovs CAS + EE 生成。 内部+ E，ovs RAS + EE输入到时钟发生电路和CBR模式确定电路，内部+ E，ovs CAS + EE输入到CBR模式确定电路。 时钟发生电路在内部+ E，RAS + EE输入时向第一和第二WL泵输出泵时钟，第一WL泵为Vpp电源供电。 如果+ E，则在+ E之前输入ovs CAS + EE，在刷新操作期间输入ovs RAS + EE，CBR模式确定电路将CBR模式信号输入到与第一WL泵一起向Vpp电源提供电荷的第二WL泵 当泵时钟和CBR模式信号被输入时。