公开(公告)号：US07940086B2

公开(公告)日：2011-05-10

申请号：US12847161

申请日：2010-07-30

申请人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

发明人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

IPC分类号： H03K19/094

CPC分类号： H04L25/028 ,  H04L25/0272

摘要： An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.

摘要翻译： 本发明的目的是实现在两个传输系统之间切换的接口电路中的输出级驱动器的面积的减小。 接口电路具有两个驱动电路和驱动控制电路，该电路可以在作为电压驱动系统和电流驱动系统的两个驱动系统之间切换。 两个驱动电路通过驱动控制电路连接到电源电位。 通过选择电路输入输入信号的两个输入信号和反相逻辑信号。 根据输入到驱动控制电路的控制信号，接口电路在电压驱动型单端传输系统和电流驱动型差动传输系统之间切换。

公开(公告)号：US20100289534A1

公开(公告)日：2010-11-18

申请号：US12847161

申请日：2010-07-30

申请人： Hiroshi SUENAGA ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

发明人： Hiroshi SUENAGA ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

IPC分类号： H03B1/00

CPC分类号： H04L25/028 ,  H04L25/0272

摘要： An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.

摘要翻译： 本发明的目的是实现在两个传输系统之间切换的接口电路中的输出级驱动器的面积的减小。 接口电路具有两个驱动电路和驱动控制电路，该电路可以在作为电压驱动系统和电流驱动系统的两个驱动系统之间切换。 两个驱动电路通过驱动控制电路连接到电源电位。 通过选择电路输入输入信号的两个输入信号和反相逻辑信号。 根据输入到驱动控制电路的控制信号，接口电路在电压驱动型单端传输系统和电流驱动型差动传输系统之间切换。

公开(公告)号：US07843224B2

公开(公告)日：2010-11-30

申请号：US12262613

申请日：2008-10-31

申请人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

发明人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

IPC分类号： H03K19/094

CPC分类号： H04L25/028 ,  H04L25/0272

摘要： An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.

摘要翻译： 本发明的目的是实现在两个传输系统之间切换的接口电路中的输出级驱动器的面积的减小。 接口电路具有两个驱动电路和驱动控制电路，该电路可以在作为电压驱动系统和电流驱动系统的两个驱动系统之间切换。 两个驱动电路通过驱动控制电路连接到电源电位。 通过选择电路输入输入信号的两个输入信号和反相逻辑信号。 根据输入到驱动控制电路的控制信号，接口电路在电压驱动型单端传输系统和电流驱动型差动传输系统之间切换。

公开(公告)号：US20090108872A1

公开(公告)日：2009-04-30

申请号：US12262613

申请日：2008-10-31

申请人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

发明人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

IPC分类号： H03K19/0175

CPC分类号： H04L25/028 ,  H04L25/0272

摘要： An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.

摘要翻译： 本发明的目的是实现在两个传输系统之间切换的接口电路中的输出级驱动器的面积的减小。 接口电路具有两个驱动电路和驱动控制电路，该电路可以在作为电压驱动系统和电流驱动系统的两个驱动系统之间切换。 两个驱动电路通过驱动控制电路连接到电源电位。 通过选择电路输入输入信号的两个输入信号和反相逻辑信号。 根据输入到驱动控制电路的控制信号，接口电路在电压驱动型单端传输系统和电流驱动型差动传输系统之间切换。

公开(公告)号：US20110115531A1

公开(公告)日：2011-05-19

申请号：US13014362

申请日：2011-01-26

申请人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

发明人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

IPC分类号： H03L7/095 ,  H03B19/00 ,  H03L7/10

CPC分类号： H03L7/10 ,  H03L7/085 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/1976

摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号 （26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

公开(公告)号：US20090274254A1

公开(公告)日：2009-11-05

申请号：US12305148

申请日：2007-06-11

申请人： Kyoko Hirata

发明人： Kyoko Hirata

IPC分类号： H04L7/00

CPC分类号： H04L7/0091 ,  H03K19/00323 ,  H04L7/0041 ,  H04L25/028

摘要： The logic block 103 generates a serial-data signal DATA using a clock signal CLK generated by a clock generator 104. Then, a skew adjusting unit 111 adjusts a delay of the serial-data signal DATA based on the phase relationship between the clock signal CLK and the serial-data signal DATA, and outputs resultant serial-data signal DATA-SK and clock signal CLK to a FF circuit 112. The FF circuit 112 shapes the serial-data signal DATA-SK using the clock signal CLK, and transmits the resultant serial-data signal DATA-FF to outside the device. Accordingly, even if jitter of a clock signal is superimposed on a data signal after signal processing, the influence of this jitter is reduced, thus providing a data transmitting device capable of transmitting a data signal to outside the device with the influence of the jitter reduced.

摘要翻译： 逻辑块103使用由时钟发生器104产生的时钟信号CLK来产生串行数据信号DATA。然后，偏斜调整单元111基于时钟信号CLK的相位关系来调整串行数据信号DATA的延迟 和串行数据信号DATA，并将合成的串行数据信号DATA-SK和时钟信号CLK输出到FF电路112.FF电路112使用时钟信号CLK对串行数据信号DATA-SK进行整形，并发送 得到串行数据信号DATA-FF到设备外部。 因此，即使信号处理后的时钟信号的抖动叠加在数据信号上，也能够减轻抖动的影响，提供能够以抖动减小的方式将数据信号发送到设备外部的数据发送装置 。

公开(公告)号：US07898305B2

公开(公告)日：2011-03-01

申请号：US12651061

申请日：2009-12-31

申请人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

发明人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

IPC分类号： H03L7/00

CPC分类号： H03L7/10 ,  H03L7/085 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/1976

摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号 （26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

公开(公告)号：US07746132B2

公开(公告)日：2010-06-29

申请号：US12066000

申请日：2006-07-27

申请人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

发明人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03L7/085 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/1976

摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号 （26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

公开(公告)号：US20100171533A1

公开(公告)日：2010-07-08

申请号：US12651061

申请日：2009-12-31

申请人： Tatsuo OKAMOTO ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

发明人： Tatsuo OKAMOTO ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03L7/085 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/1976

摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号 （26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

公开(公告)号：US20090153203A1

公开(公告)日：2009-06-18

申请号：US12066000

申请日：2006-07-27

申请人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

发明人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03L7/085 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/1976

摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号 （26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。