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    Semiconductor memory device equipped with error correction circuit
    1.
    发明申请
    Semiconductor memory device equipped with error correction circuit 有权
    半导体存储器件配有纠错电路

    公开(公告)号：US20050229080A1

    公开(公告)日：2005-10-13

    申请号：US11130059

    申请日：2005-05-17

    申请人： Hiroshi Takahashi ,  Akihiro Takegama ,  Osamu Handa ,  Hiroshi Kimizuka

    发明人： Hiroshi Takahashi ,  Akihiro Takegama ,  Osamu Handa ,  Hiroshi Kimizuka

    IPC分类号： H03M13/19 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  H03M13/00

    CPC分类号： G06F11/1008

    摘要： The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.

    摘要翻译： 本发明的目的是提供一种配备有纠错电路200的半导体存储器件，其特征在于可以在不增加电路尺寸和功耗的情况下执行存储数据中的错误校正，并且不降低操作速度。 纠错码EC对应于与存储在主存储器110中的主数据分离的子存储器120中存储的数据。在读取模式中，主数据和纠错码分别从主存储器和子存储器读取。 基于这些数据，生成用于校正读取数据中的错误的纠错码。 纠错电路300纠正主数据中的错误。 通过将错误校正码存储在与主存储器不同的子存储器中并选择主存储器和子存储器的适当布局，可以增加纠错码的读取速度并且抑制由 纠错。

    Semiconductor memory device equipped with error correction circuit
    2.
    发明授权
    Semiconductor memory device equipped with error correction circuit 有权
    半导体存储器件配有纠错电路

    公开(公告)号：US07426683B2

    公开(公告)日：2008-09-16

    申请号：US11130059

    申请日：2005-05-17

    申请人： Hiroshi Takahashi ,  Akihiro Takegama ,  Osamu Handa ,  Hiroshi Kimizuka

    发明人： Hiroshi Takahashi ,  Akihiro Takegama ,  Osamu Handa ,  Hiroshi Kimizuka

    IPC分类号： G06F11/00 ,  H03M13/00

    CPC分类号： G06F11/1008

    摘要： The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.

    摘要翻译： 本发明的目的是提供一种配备有纠错电路200的半导体存储器件，其特征在于可以在不增加电路尺寸和功耗的情况下执行存储数据中的错误校正，并且不降低操作速度。 纠错码EC对应于与存储在主存储器110中的主数据分离的子存储器120中存储的数据。在读取模式中，主数据和纠错码分别从主存储器和子存储器读取。 基于这些数据，生成用于校正读取数据中的错误的纠错码。 纠错电路300纠正主数据中的错误。 通过将错误校正码存储在与主存储器不同的子存储器中并选择主存储器和子存储器的适当布局，可以增加纠错码的读取速度并抑制由 纠错。

    Semiconductor memory device equipped with error correction circuit
    3.
    发明授权
    Semiconductor memory device equipped with error correction circuit 有权

    公开(公告)号：US07069493B2

    公开(公告)日：2006-06-27

    申请号：US10245209

    申请日：2002-09-17

    申请人： Hiroshi Takahashi ,  Akihiro Takegama ,  Osamu Handa ,  Hiroshi Kimizuka

    发明人： Hiroshi Takahashi ,  Akihiro Takegama ,  Osamu Handa ,  Hiroshi Kimizuka

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1008

    摘要： The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.

    High speed semiconductor circuit having low power consumption
    4.
    发明授权
    High speed semiconductor circuit having low power consumption 有权
    具有低功耗的高速半导体电路

    公开(公告)号：US06741098B2

    公开(公告)日：2004-05-25

    申请号：US09884662

    申请日：2001-06-19

    申请人： Hiroshi Takahashi ,  Yutaka Toyonoh ,  Akihiro Takegama ,  Osamu Handa ,  Rimon Ikeno ,  Kaoru Awaka ,  Tsuyoshi Tanaka

    发明人： Hiroshi Takahashi ,  Yutaka Toyonoh ,  Akihiro Takegama ,  Osamu Handa ,  Rimon Ikeno ,  Kaoru Awaka ,  Tsuyoshi Tanaka

    IPC分类号： H03K301

    CPC分类号： H01L27/0928 ,  H03K19/0016

    摘要： A semiconductor circuit which can restrain increase in manufacturing cost and layout area to a minimum level and can realize high speed and low power consumption. Bias voltages with different levels are generated corresponding to a mode control signal by a bias voltage supply circuit comprising PMOS transistors P2 and P3 which have different voltages applied to the respective sources and the mode control signal input to the gates. The generated bias voltages are supplied to the n-wells of PMOS transistors. During operation, a bias voltage that is almost the same as the operation voltage is applied to the n-wells of PMOS transistors. During standby, a bias voltage higher than the operation voltage is supplied to the aforementioned n-wells of PMOS transistors. In this way, the driving currents of the transistors can be kept at a high level during operation, while leakage currents of the transistors can be restrained during standby. Consequently, high speed and low power consumption can be realized.

    摘要翻译： 一种可以将制造成本和布局面积增加到最低限度的半导体电路，并且可以实现高速度和低功耗。 通过包括施加到各个源的不同电压的PMOS晶体管P2和P3的偏置电压供给电路和输入到门的模式控制信号，对应于模式控制信号产生具有不同电平的偏置电压。 产生的偏置电压被提供给PMOS晶体管的n阱。 在操作期间，将与工作电压几乎相同的偏置电压施加到PMOS晶体管的n阱。 在待机期间，将高于工作电压的偏置电压提供给PMOS晶体管的上述n阱。 以这种方式，晶体管的驱动电流可以在工作期间保持在高电平，同时可以在待机期间抑制晶体管的漏电流。 因此，可以实现高速度和低功耗。

    Semiconductor integrated circuit
    5.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06603328B2

    公开(公告)日：2003-08-05

    申请号：US09974696

    申请日：2001-10-10

    申请人： Hiroshi Takahashi ,  Osamu Handa ,  Akihiro Takegama ,  Yutaka Toyonoh ,  Kaoru Awaka ,  Rimon Ikeno ,  Tsuyoshi Tanaka

    发明人： Hiroshi Takahashi ,  Osamu Handa ,  Akihiro Takegama ,  Yutaka Toyonoh ,  Kaoru Awaka ,  Rimon Ikeno ,  Tsuyoshi Tanaka

    IPC分类号： G01R3126

    CPC分类号： G01R31/31721 ,  G01R31/3008 ,  H03K19/00361

    摘要： The objective of this invention is to provide a type of semiconductor integrated circuit which can lessen solution in the circuit area to the minimum necessary level, and can lessen the leakage current in the standby state so as to cut the power consumption, and which allows Iddq test to determine whether it is passed or defective. Logic circuit 10 composed of low threshold voltage transistors and switching circuit 20 composed of transistors having the standard threshold voltage are set. In the operation, the switching circuit is turned ON, and a driving current is fed to logic circuit 10. On the other hand, in the standby mode, the switching circuit is turned OFF, and the path of the leakage current is cut off to lessen generation of the leakage current. In the case of Iddq test, different bulk bias voltages are applied to the channel regions of PMOS transistors and NMOS transistors from an IC tester through pads P1 and P2. In this way, the leakage current can be lessened on a low level, and whether the semiconductor integrated circuit is passed or defective can be judged from the results of the current measurement.

    摘要翻译： 本发明的目的是提供一种半导体集成电路，其可以将电路区域中的解决方案减少到最小必要水平，并且可以减少待机状态下的泄漏电流，从而降低功耗，并且允许Iddq 测试以确定是否通过或有缺陷。 设置由低阈值电压晶体管构成的逻辑电路10和由具有标准阈值电压的晶体管构成的开关电路20。 在操作中，开关电路导通，驱动电流被馈送到逻辑电路10.另一方面，在待机模式下，开关电路断开，漏电流的路径被切断为 减少漏电流的产生。 在Iddq测试的情况下，不同的体偏置电压通过焊盘P1和P2从IC测试器施加到PMOS晶体管和NMOS晶体管的沟道区。 以这种方式，可以根据电流测量的结果来判断漏电流是否在低电平，并且半导体集成电路是否通过还是有缺陷。

    Suppressing the leakage current in an integrated circuit
    6.
    发明申请
    Suppressing the leakage current in an integrated circuit 审中-公开
    抑制集成电路中的漏电流

    公开(公告)号：US20050068059A1

    公开(公告)日：2005-03-31

    申请号：US10962893

    申请日：2004-10-12

    申请人： Hiroshi Takahashi ,  Akihiro Takegama ,  Yutaka Toyonoh ,  Kaoru Awaka ,  Tsuyoshi Tanaka ,  Rimon Ikeno

    发明人： Hiroshi Takahashi ,  Akihiro Takegama ,  Yutaka Toyonoh ,  Kaoru Awaka ,  Tsuyoshi Tanaka ,  Rimon Ikeno

    IPC分类号： H01L21/822 ,  G11C5/14 ,  H01L27/04 ,  H01L31/0336 ,  H03K17/687 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0948

    CPC分类号： H03K19/00315 ,  G11C5/14 ,  H03K19/0016

    摘要： A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability. While in a standby status, a voltage equal to source voltage Vdd is applied to the gate of transistor MP0, a voltage lower than the source voltage is applied to the source, and bulk bias voltage VB equal to or higher than source voltage Vdd is applied to the channel region in order to minimize the drain current of transistor MP0, so that current path of logic circuit 10 is cut off, and the occurrence of leakage current is suppressed.

    摘要翻译： 一种半导体集成电路，其中电路面积可以最小化，并且在待机状态期间可以可靠地检测缺陷，同时保持栅氧化膜的可靠性。 开关电路20设置在逻辑电路10和源电压Vdd供电端子之间。 在工作状态下，将0V电压施加到开关电路20的晶体管MP0的栅极，并将等于或略低于源极电压Vdd的偏置电压VB施加到其沟道区，以便降低晶体管的阈值电压 MP0并提高其目前的驾驶能力。 在待机状态下，将等于源极电压Vdd的电压施加到晶体管MP0的栅极，将低于源极电压的电压施加到源极，施加等于或高于源极电压Vdd的体偏置电压Vdd 到沟道区域，以使晶体管MP0的漏极电流最小化，使得逻辑电路10的电流路径被切断，并且抑制了泄漏电流的发生。

    Multiply-accumulate modules and parallel multipliers and methods of designing multiply-accumulate modules and parallel multipliers
    8.
    发明授权
    Multiply-accumulate modules and parallel multipliers and methods of designing multiply-accumulate modules and parallel multipliers 有权
    乘法累加模块和并行乘法器以及设计乘法累加模块和并行乘法器的方法

    公开(公告)号：US07315879B2

    公开(公告)日：2008-01-01

    申请号：US09963480

    申请日：2001-09-27

    申请人： Kaoru Awaka ,  Hiroshi Takahashi ,  Shigetoshi Muramatsu ,  Akihiro Takegama

    发明人： Kaoru Awaka ,  Hiroshi Takahashi ,  Shigetoshi Muramatsu ,  Akihiro Takegama

    IPC分类号： G06F15/00

    CPC分类号： G06F7/5318 ,  G06F7/49921 ,  G06F7/5332 ,  G06F7/5443

    摘要： A multiply-accumulate module (100) includes a multiply-accumulate core (120), which includes a plurality of Booth encoder cells (104a). The multiply-accumulate core (120) also includes a plurality of Booth decoder cells (110a) connected to at least one of the Booth encoder cells (104a) and a plurality of Wallace tree cells (112a) connected to at least one of the Booth decoder cells (110a). Moreover, at least one first Wallace tree cell (112a1) or at least one first Booth decoder cell (110a1), or any combination thereof, includes a first plurality of transistors, and at least one second Wallace tree cell (112a2) or at least one second Booth decoder cell (110a2), or any combination thereof, includes a second plurality of transistors. In addition, at least one critical path of the multiply-accumulate module (100) includes the at least one first cell and a width of at least one of the first plurality of transistors is greater than a width of at least one of the second plurality of transistors.

    摘要翻译： 乘法累加模块（100）包括乘法累加核（120），其包括多个布斯编码器单元（104a）。 多重累加核心（120）还包括多个布尔解码器单元（110a），其连接到至少一个布斯编码器单元（104a）和多个连接至至少一个的华莱士树单元（112a） 的布斯解码器单元（110a）。 此外，至少一个第一华莱士树单元（112a）或至少一个第一布尔解码器单元（110a 1）或其任何组合包括第一多个晶体管，以及至少一个第二华莱士树单元（112a） 一个2）或至少一个第二布尔解码器单元（110a2）或其任何组合包括第二多个晶体管。 另外，乘法累加模块（100）的至少一个关键路径包括至少一个第一单元，并且第一多个晶体管中的至少一个晶体管的宽度大于第二多个晶体管中的至少一个的宽度 的晶体管。

    Ratio circuit
    10.
    发明授权
    Ratio circuit 有权

    公开(公告)号：US06410966B1

    公开(公告)日：2002-06-25

    申请号：US09880205

    申请日：2001-06-13

    申请人： Hiroshi Takahashi ,  Yutaka Toyonoh ,  Yasumasa Ikezaki ,  Tohru Urasaki ,  Akihiro Takegama

    发明人： Hiroshi Takahashi ,  Yutaka Toyonoh ,  Yasumasa Ikezaki ,  Tohru Urasaki ,  Akihiro Takegama

    IPC分类号： H01L2976

    摘要： The purpose of this invention is to ensure an active use of the inverse short-channel effect in the ratio circuit and to guarantee stable operation at low power source voltage. In this ratio circuit, N-channel MOS transistor 12 of CMOS circuit 10 on one side forms the drive element, while P-channel MOS transistor 18 of CMOS circuit 16 on the other side forms the load element. Said N-channel MOS transistor 12 on the drive side and P-channel MOS transistor 16 on the load side have their drain terminals electrically connected to each other through transfer gate 22 made of N-channel MOS transistor. MOS transistor 12 on the drive side has a single channel CHa with the inverse short-channel effect. MOS transistor 18 on the load side has plural, e.g., two, channels CHb1 and CHb2, connected in tandem, each of which displays the inverse short-channel effect.