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    Apparatus for high-speed packet switching in a broadband ISDN
    3.
    发明授权
    Apparatus for high-speed packet switching in a broadband ISDN 失效
    用于宽带ISDN中高速分组交换的装置

    公开(公告)号：US5696759A

    公开(公告)日：1997-12-09

    申请号：US554038

    申请日：1995-11-06

    申请人： Hiroshi Tomonaga ,  Naoki Matsuoka ,  Masaaki Kawai

    发明人： Hiroshi Tomonaga ,  Naoki Matsuoka ,  Masaaki Kawai

    IPC分类号： H04Q3/42 ,  H04L12/70 ,  H04L12/813 ,  H04L12/931 ,  H04Q3/00 ,  H04L12/56 ,  H04L12/26

    CPC分类号： H04L12/5601 ,  H04L49/3009 ,  H04L49/3081 ,  H04L2012/5619 ,  H04L2012/5625 ,  H04L2012/5636 ,  H04L2012/5639 ,  H04L2012/5647 ,  H04L2012/5672

    摘要： A switching equipment accommodates lines and includes a line interface for processing data from the line on the unit of cell. The line interface has a basic processing unit and an additional processing unit. The basic processing unit performs a basic process on the cell. The additional processing unit separated from the basic processing unit but disconnectably connected to the basic processing unit executes an additional process on the cell. The additional processing unit includes a plurality of processing blocks for effecting a plurality of additional processes on the cells. Each processing block is individually disconnectably connected to the basic processing unit. The basic processing unit includes a selecting portion for selecting, when one or more processing blocks within the additional processing unit are connected, the connected processing blocks and performing the additional process on the cell.

    摘要翻译： 交换设备容纳线路，并且包括用于处理来自单元单元的线路的数据的线路接口。 线路接口具有基本处理单元和附加处理单元。 基本处理单元对单元执行基本处理。 与基本处理单元分离但与基本处理单元可断开连接的附加处理单元在单元上执行附加处理。 附加处理单元包括用于在单元上进行多个附加处理的多个处理块。 每个处理块单独地可拆卸地连接到基本处理单元。 基本处理单元包括：选择部分，用于当连接附加处理单元内的一个或多个处理块时，选择所连接的处理块并在该单元上执行附加处理。

    Input line interface device and packet communication device
    4.
    发明授权
    Input line interface device and packet communication device 有权
    输入线路接口设备和分组通信设备

    公开(公告)号：US07366165B2

    公开(公告)日：2008-04-29

    申请号：US10079082

    申请日：2002-02-19

    申请人： Kenichi Kawarai ,  Masakatsu Nagata ,  Hiroshi Tomonaga ,  Naoki Matsuoka ,  Tsuguo Kato

    发明人： Kenichi Kawarai ,  Masakatsu Nagata ,  Hiroshi Tomonaga ,  Naoki Matsuoka ,  Tsuguo Kato

    IPC分类号： H04Q11/00

    CPC分类号： H04L49/9094 ,  H04L12/46 ,  H04L45/60 ,  H04L47/2441 ,  H04L49/30 ,  H04L49/90

    摘要： An input line interface device that is used to accommodate packets from a high-speed line efficiently and to reduce a processing load on a back stage caused by routing control. A packet allotting section divides a variable-length packet, allots divided packets to parallel lines, and outputs the packets. A flow group classifying section classifies the packets into flow groups on each of the parallel lines. A sequence number giving section gives the packets sequence numbers corresponding to or independent of the flow groups. A buffering section stores the packets to which the sequence numbers have been given in a buffer or reads out them from the buffer to exercise sequence control over the packets in the flow groups. A flow separating switch separates the packets according to the flow groups and outputs the packets.

    摘要翻译： 一种输入线接口装置，用于有效地适应来自高速线路的分组，并减少由路由控制引起的后台处理负担。 分组分配部分分割可变长度分组，将分组分配给并行，并输出分组。 流组分类部分将每个并行线路上的分组分组为流组。 序列号给出部分给出与流组相对应或独立于流组的分组序列号。 缓冲部分将缓冲器中已经给出序列号的分组存储在缓冲器中，或者从缓冲器中读出它们以对流组中的分组进行序列控制。 流分离交换机根据流组分离报文，并输出报文。

    Packet switch device and scheduling control method
    5.
    发明授权
    Packet switch device and scheduling control method 失效
    分组交换机和调度控制方法

    公开(公告)号：US06920145B2

    公开(公告)日：2005-07-19

    申请号：US09759181

    申请日：2001-01-12

    申请人： Naoki Matsuoka ,  Hiroshi Tomonaga ,  Kenichi Kawarai

    发明人： Naoki Matsuoka ,  Hiroshi Tomonaga ,  Kenichi Kawarai

    IPC分类号： H04L12/931 ,  H04L12/937 ,  H04L12/56

    CPC分类号： H04L49/608 ,  H04L49/205 ,  H04L49/254 ,  H04L49/30 ,  H04L49/3063 ,  H04L49/503 ,  H04L49/508 ,  H04L2012/5679

    摘要： A packet switch device having a plurality of input buffers; a packet switch; a plurality of schedulers, having a pipeline scheduling process module wherein a plurality of time units corresponding to the number of output lines is spent in scheduled sending process of the fixed length packets from the input buffer, and wherein the scheduled sending process is executed in a number of processes, in parallel, the number of processes corresponding to the number of the input lines, having a sending status management module wherein sending status of the fixed length packets which constitute one frame is managed for each of the input lines, and provided corresponding to any of the output lines; and at least one result notification module for notifying the input buffer of result information from the scheduled sending process performed by each of the plurality of schedulers. Further, in the scheduled sending process executed in a number of processes, in parallel, the device does not select the input line sending the fixed length packets corresponding to the same frame, and, after determining a selection, the device maintains the selection of the same input line until the completion of sending the fixed length packets corresponding to the same frame.

    摘要翻译： 一种具有多个输入缓冲器的分组交换设备; 分组交换机 多个调度器，其具有流水线调度处理模块，其中与输出线数相对应的多个时间单元在来自输入缓冲器的固定长度分组的调度发送过程中被消耗，并且其中调度发送过程以 并行处理对应于输入线数量的处理次数，具有发送状态管理模块，其中为每个输入行管理构成一帧的固定长度分组的发送状态，并且提供相应的 到任何输出线; 以及至少一个结果通知模块，用于从所述多个调度器中的每个调度器执行的所调度的发送处理通知结果信息的输入缓冲器。 此外，在多个处理中执行的调度发送处理中，并行地，设备不选择发送对应于同一帧的固定长度分组的输入行，并且在确定选择之后，设备保持对 相同的输入行直到完成发送对应于同一帧的固定长度数据包。

    Bandwidth control apparatus
    6.
    发明授权
    Bandwidth control apparatus 失效
    带宽控制装置

    公开(公告)号：US06687225B1

    公开(公告)日：2004-02-03

    申请号：US09421465

    申请日：1999-10-19

    申请人： Kenichi Kawarai ,  Hiroshi Tomonaga ,  Naoki Matsuoka ,  Naotoshi Watanabe ,  Yasuhiro Ooba ,  Hichiro Hayami

    发明人： Kenichi Kawarai ,  Hiroshi Tomonaga ,  Naoki Matsuoka ,  Naotoshi Watanabe ,  Yasuhiro Ooba ,  Hichiro Hayami

    IPC分类号： H04L1256

    CPC分类号： H04Q11/0478 ,  H04L12/5601 ,  H04L12/5602 ,  H04L2012/5625 ,  H04L2012/5632 ,  H04L2012/5651 ,  H04L2012/568

    摘要： The invention relates to a bandwidth control apparatus in ATM equipment, for inserting management cells such as OAM cells, the control apparatus being configured to secure a bandwidth for the insertion of a management cell such as an OAM cell when the need arises, while guaranteeing the service quality of user cells, thereby making effective use of network resources for a best effort service such as ABR or UBR. The bandwidth control apparatus comprises a cell insertion block 1-10 for inserting a management cell such as an OAM cell and a shaping block 1-20 for performing user cell shaping, wherein the cell insertion block 1-10 issues an empty cell request when a cell insertion request occurs, the shaping block 1-20, upon receiving the empty cell insertion request, inserts an empty cell in a user cell stream being output from a shaping buffer 1-22, and the cell insertion block 1-10 writes a management cell such as an OAM cell over the empty cell inserted on a cell highway 1-30, thus sending the management cell out on the cell highway 1-30.

    摘要翻译： 本发明涉及一种ATM设备中的带宽控制装置，用于插入诸如OAM小区的管理小区，该控制装置被配置为在需要时保证用于插入诸如OAM小区之类的管理小区的带宽，同时保证 用户单元的服务质量，从而有效利用网络资源实现最佳服务，如ABR或UBR。 带宽控制装置包括用于插入诸如OAM小区的管理小区的小区插入块1-10和用于进行用户小区整形的整形块1-20，其中，当小区插入块1-10发出空单元请求时， 单元插入请求发生时，整形块1-20在接收到空单元插入请求时，将其从一个整形缓冲器1-22输出的用户单元流中插入一个空单元，并且单元插入块1-10写入管理 小区，例如插入单元高速公路1-30上的空单元上的OAM单元，从而将单元高速公路1-30上的管理单元发送出去。

    Packet switch device
    9.
    发明授权
    Packet switch device 失效
    分组交换设备

    公开(公告)号：US07227861B2

    公开(公告)日：2007-06-05

    申请号：US09805545

    申请日：2001-03-13

    申请人： Hiroshi Tomonaga ,  Masakatsu Nagata ,  Kenichi Kawarai ,  Naoki Matsuoka ,  Kenichi Okabe ,  Shiro Uriu

    发明人： Hiroshi Tomonaga ,  Masakatsu Nagata ,  Kenichi Kawarai ,  Naoki Matsuoka ,  Kenichi Okabe ,  Shiro Uriu

    IPC分类号： H04L12/56

    CPC分类号： H04Q11/0421 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13296

    摘要： Packets input from input HWs #0 to #3 to a packet switch device are buried in time slots A through D. The packet switch device alternately switches the input packets in units of time slots, and inputs the packets to two 4×4 switches. The 4×4 switches make normal switching, and distribute the packets to respective output ports. Then, the packets output from the two 4×4 switches after being switched are alternately multiplexed, and output to output HWs #0 through #3. By making switching in units of packets as described above, a process overhead is prevented from being increased, and also expansion can be easily made. Besides, hardware scale can be made small.

    摘要翻译： 从输入HW＃0到＃3输入到分组交换设备的分组被掩埋在时隙A到D中。分组交换设备以时隙为单位交替地切换输入分组，并将分组输入到两个4×4交换机。 4x4交换机进行正常交换，并将数据包分配到相应的输出端口。 然后，在切换之后从两个4×4交换机输出的分组交替复用，并输出到输出HW＃0至＃3。 通过如上所述进行分组的切换，防止了处理开销的增加，并且也可以容易地进行扩展。 此外，硬件规模可以减小。