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公开(公告)号：US07058751B2
公开(公告)日：2006-06-06
申请号：US09942980
申请日：2001-08-30
申请人： Kenichi Kawarai , Hiroshi Tomonaga , Naoki Matsuoka , Masakatsu Nagata , Tsuguo Kato , Tetsuaki Wakabayashi
发明人： Kenichi Kawarai , Hiroshi Tomonaga , Naoki Matsuoka , Masakatsu Nagata , Tsuguo Kato , Tetsuaki Wakabayashi
IPC分类号： G06F13/00
CPC分类号： H04L49/201 , H04L49/101 , H04L49/506
摘要： The packet switch performs a scheduling process by selecting a unicast packet or a multicast packet to be output from each of N input buffers such that input lines and output lines cannot conflict each other for a unicast packet, and such that the input lines cannot conflict each other for the multicast packet.
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公开(公告)号：US06947413B2
公开(公告)日：2005-09-20
申请号：US09942314
申请日：2001-08-29
IPC分类号： H04L12/70 , H04L12/761 , H04L12/931 , H04L12/947 , H04L12/28
CPC分类号： H04L49/101 , H04L49/201 , H04L49/25
摘要： A switching apparatus that is used for high-speed large-capacity routing and a communication apparatus and communication system that are used for an efficient recursive multicast. A matrix switch performs self-routing on a packet on the basis of a tag including output route information set in the packet. Selectors are located so as to correspond to N output ports P#1 through P#N of the matrix switch and perform N-to-one selection control. Setting registers hold selection information used by the selectors to select a signal.
摘要翻译： 用于高速大容量路由的交换装置和用于高效递归组播的通信装置和通信系统。 矩阵开关基于包括在分组中设置的输出路由信息的标签在分组上执行自路由。 选择器被定位成对应于矩阵开关的N个输出端口P＃1到P＃N，并执行N-1选择控制。 设置寄存器保存选择器使用的选择信息来选择一个信号。
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公开(公告)号：US08560812B2
公开(公告)日：2013-10-15
申请号：US12783958
申请日：2010-05-20
CPC分类号： G06F9/3851
摘要： A multithread execution device includes: a program memory in which a plurality of programs are stored; an instruction issue unit that issues an instruction retrieved from the program memory; an instruction execution unit that executes the instruction; a target execution speed information memory that stores target execution speed information of the instruction; an execution speed monitor that monitors an execution speed of the instruction; a feedback control unit that commands the instruction issue unit to issue the instruction such that the execution speed of the instruction approximately corresponds to the target execution speed information.
摘要翻译： 多线程执行装置包括：存储多个程序的程序存储器; 发出从程序存储器检索的指令的指令发布单元; 执行指令的指令执行单元; 目标执行速度信息存储器，存储指令的目标执行速度信息; 执行速度监视器，其监视指令的执行速度; 命令指令发布单元发出指令的反馈控制单元，使得指令的执行速度大致对应于目标执行速度信息。
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公开(公告)号：US20100312992A1
公开(公告)日：2010-12-09
申请号：US12783958
申请日：2010-05-20
CPC分类号： G06F9/3851
摘要： A multithread execution device includes: a program memory in which a plurality of programs are stored; an instruction issue unit that issues an instruction retrieved from the program memory; an instruction execution unit that executes the instruction; a target execution speed information memory that stores target execution speed information of the instruction; an execution speed monitor that monitors an execution speed of the instruction; a feedback control unit that commands the instruction issue unit to issue the instruction such that the execution speed of the instruction approximately corresponds to the target execution speed information.
摘要翻译： 多线程执行装置包括：存储多个程序的程序存储器; 发出从程序存储器检索的指令的指令发布单元; 执行指令的指令执行单元; 目标执行速度信息存储器，存储指令的目标执行速度信息; 执行速度监视器，其监视指令的执行速度; 命令指令发布单元发出指令的反馈控制单元，使得指令的执行速度大致对应于目标执行速度信息。
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公开(公告)号：US09222430B2
公开(公告)日：2015-12-29
申请号：US12983487
申请日：2011-01-03
CPC分类号： F02D41/26 , G06F1/06 , G06F1/3203 , H03L7/16 , Y02D10/126
摘要： A multicore processor according to the invention has a plurality of cores. The plurality of cores are configured to operate at an operation clock with a frequency varying periodically with the same period, and a variation phase of a frequency of the operation clock of each core of the plurality of cores is shifted by a predetermined amount among the plurality of cores.
摘要翻译： 根据本发明的多核处理器具有多个核心。 所述多个核心被配置为在周期性变化的周期的周期性变化的操作时钟下工作，并且所述多个核心的每个核心的操作时钟的频率的变化相位偏移预定量 的核心。
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6.发明授权Address release method, and common buffering device for ATM switching system which employs the same method 失效地址释放方法和采用相同方法的ATM交换系统的通用缓冲装置公开(公告)号：US06789176B2
公开(公告)日：2004-09-07
申请号：US09286332
申请日：1999-04-05
IPC分类号： G06F1206
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/203 , H04L49/255 , H04L2012/5681
摘要： In a common buffering device with a simple arrangement, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call. For an ATM cell which is to be transmitted to a specific line, a write address is set in a common buffer memory, and the ATM cell is written at the write address. The ATM cell is read from an address which corresponds to the write address, and is transmitted to the specific line. Then, the pertinent write address is released. In a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.
摘要翻译： 在具有简单布置的公共缓冲装置中，在接收到多地址呼叫时，可以从缓冲存储器高效地释放写入地址。 对于要发送到特定线路的ATM信元，在公共缓冲存储器中设置写入地址，并且将ATM信元写入写入地址。 ATM单元从对应于写入地址的地址读取，并被发送到特定的行。 然后，释放相关的写入地址。 在写入表中输入多个多地址线，在公共缓冲设备中以特定地址写入的ATM信元可以跨多路地址线进行组播。 每当从特定地址读取ATM信元时，将读取控制表中的ATM信元的发送指定行与设置在写入控制表中的多地址线进行比较。 当行匹配时，释放写入控制表中设置的ATM信元的写入地址。
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