公开(公告)号：US07058751B2

公开(公告)日：2006-06-06

申请号：US09942980

申请日：2001-08-30

申请人： Kenichi Kawarai ,  Hiroshi Tomonaga ,  Naoki Matsuoka ,  Masakatsu Nagata ,  Tsuguo Kato ,  Tetsuaki Wakabayashi

发明人： Kenichi Kawarai ,  Hiroshi Tomonaga ,  Naoki Matsuoka ,  Masakatsu Nagata ,  Tsuguo Kato ,  Tetsuaki Wakabayashi

IPC分类号： G06F13/00

CPC分类号： H04L49/201 ,  H04L49/101 ,  H04L49/506

摘要： The packet switch performs a scheduling process by selecting a unicast packet or a multicast packet to be output from each of N input buffers such that input lines and output lines cannot conflict each other for a unicast packet, and such that the input lines cannot conflict each other for the multicast packet.

公开(公告)号：US07366165B2

公开(公告)日：2008-04-29

申请号：US10079082

申请日：2002-02-19

申请人： Kenichi Kawarai ,  Masakatsu Nagata ,  Hiroshi Tomonaga ,  Naoki Matsuoka ,  Tsuguo Kato

发明人： Kenichi Kawarai ,  Masakatsu Nagata ,  Hiroshi Tomonaga ,  Naoki Matsuoka ,  Tsuguo Kato

IPC分类号： H04Q11/00

CPC分类号： H04L49/9094 ,  H04L12/46 ,  H04L45/60 ,  H04L47/2441 ,  H04L49/30 ,  H04L49/90

摘要： An input line interface device that is used to accommodate packets from a high-speed line efficiently and to reduce a processing load on a back stage caused by routing control. A packet allotting section divides a variable-length packet, allots divided packets to parallel lines, and outputs the packets. A flow group classifying section classifies the packets into flow groups on each of the parallel lines. A sequence number giving section gives the packets sequence numbers corresponding to or independent of the flow groups. A buffering section stores the packets to which the sequence numbers have been given in a buffer or reads out them from the buffer to exercise sequence control over the packets in the flow groups. A flow separating switch separates the packets according to the flow groups and outputs the packets.

摘要翻译： 一种输入线接口装置，用于有效地适应来自高速线路的分组，并减少由路由控制引起的后台处理负担。 分组分配部分分割可变长度分组，将分组分配给并行，并输出分组。 流组分类部分将每个并行线路上的分组分组为流组。 序列号给出部分给出与流组相对应或独立于流组的分组序列号。 缓冲部分将缓冲器中已经给出序列号的分组存储在缓冲器中，或者从缓冲器中读出它们以对流组中的分组进行序列控制。 流分离交换机根据流组分离报文，并输出报文。

公开(公告)号：US07023865B2

公开(公告)日：2006-04-04

申请号：US09942979

申请日：2001-08-30

申请人： Naoki Matsuoka ,  Hiroshi Tomonaga ,  Kenichi Kawarai ,  Masakatsu Nagata

发明人： Naoki Matsuoka ,  Hiroshi Tomonaga ,  Kenichi Kawarai ,  Masakatsu Nagata

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L47/28 ,  H04L47/50 ,  H04L47/521 ,  H04L47/6225 ,  H04L49/3018 ,  H04L49/503

摘要： A packet switch which can cyclically use α scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by α scheduler sections independently performing scheduling processes is disclosed.

公开(公告)号：US07227861B2

公开(公告)日：2007-06-05

申请号：US09805545

申请日：2001-03-13

申请人： Hiroshi Tomonaga ,  Masakatsu Nagata ,  Kenichi Kawarai ,  Naoki Matsuoka ,  Kenichi Okabe ,  Shiro Uriu

发明人： Hiroshi Tomonaga ,  Masakatsu Nagata ,  Kenichi Kawarai ,  Naoki Matsuoka ,  Kenichi Okabe ,  Shiro Uriu

IPC分类号： H04L12/56

CPC分类号： H04Q11/0421 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13296

摘要： Packets input from input HWs #0 to #3 to a packet switch device are buried in time slots A through D. The packet switch device alternately switches the input packets in units of time slots, and inputs the packets to two 4×4 switches. The 4×4 switches make normal switching, and distribute the packets to respective output ports. Then, the packets output from the two 4×4 switches after being switched are alternately multiplexed, and output to output HWs #0 through #3. By making switching in units of packets as described above, a process overhead is prevented from being increased, and also expansion can be easily made. Besides, hardware scale can be made small.

摘要翻译： 从输入HW＃0到＃3输入到分组交换设备的分组被掩埋在时隙A到D中。分组交换设备以时隙为单位交替地切换输入分组，并将分组输入到两个4×4交换机。 4x4交换机进行正常交换，并将数据包分配到相应的输出端口。 然后，在切换之后从两个4×4交换机输出的分组交替复用，并输出到输出HW＃0至＃3。 通过如上所述进行分组的切换，防止了处理开销的增加，并且也可以容易地进行扩展。 此外，硬件规模可以减小。

公开(公告)号：US07046685B1

公开(公告)日：2006-05-16

申请号：US09460898

申请日：1999-12-14

申请人： Naoki Matsuoka ,  Kenichi Kawarai ,  Hiroshi Tomonaga ,  Tsuguo Kato

发明人： Naoki Matsuoka ,  Kenichi Kawarai ,  Hiroshi Tomonaga ,  Tsuguo Kato

IPC分类号： H04L12/56 ,  H04L12/54 ,  H04L12/43 ,  H04J7/00

CPC分类号： H04L49/1553 ,  H04L12/5601 ,  H04L41/0896 ,  H04L47/50 ,  H04L47/6225 ,  H04L49/3045 ,  H04L2012/5679 ,  H04L2012/5681

摘要： A scheduling system is capable of causing no deterioration of characteristics even under equal and unequal loads, eliminating the necessity for high-speed repetitive scheduling and complicated arithmetic processes, simplifying its architecture and having its processing speed which does not depend upon a device capability. For attaining this system, an inter-highway pointer is updated to an adjacent line (rightward) when the scheduling for all the lines are finished. If the inter-highway pointer is updated N-times in the same direction (clockwise), the same pointer is updated to an adjacent line in a reverse direction (counterclockwise) in next N-processes of scheduling.

摘要翻译： 调度系统即使在相等和不相等的负载下也不会导致特性恶化，消除了高速重复调度和复杂运算过程的必要性，简化了其架构并且具有不依赖于设备能力的处理速度。 为了实现该系统，当所有行的调度完成时，将将公路间指针更新为相邻行（向右）。 如果公路间指针以相同方向（顺时针）N次更新，则在下一个N个调度处理中，相同的指针在相反方向（逆时针）更新为相邻的行。

公开(公告)号：US07016366B2

公开(公告)日：2006-03-21

申请号：US09813226

申请日：2001-03-20

申请人： Kenichi Kawarai ,  Hiroshi Tomonaga ,  Naoki Matsuoka ,  Tsuguo Kato

发明人： Kenichi Kawarai ,  Hiroshi Tomonaga ,  Naoki Matsuoka ,  Tsuguo Kato

IPC分类号： H04L12/28

CPC分类号： H04L49/30 ,  H04L47/10 ,  H04L47/15 ,  H04L47/20 ,  H04L47/2433 ,  H04L47/2441 ,  H04L47/29 ,  H04L47/30 ,  H04L47/32 ,  H04L47/50 ,  H04L47/60 ,  H04L47/627 ,  H04L49/101 ,  H04L49/201 ,  H04L49/205 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/3045 ,  H04L49/3063 ,  H04L49/3072 ,  H04L49/3081 ,  H04L49/503 ,  H04L49/608 ,  H04L2012/5647 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5679 ,  H04L2012/5682

摘要： To achieve QoS control, drop control and multicast control of a variable-length packet at high speed in small scale hardware, a packet divider divides a variable-length packet into fixed-length packets, and an input buffer section stores the divided fixed-length packets into queues by output lines and by QoS classes. A large number of QoS classes are mapped into only two kinds of classes including a guaranteed bandwidth class for which an assigned bandwidth is guaranteed and a best effort class for which a surplus bandwidth is allocated, thereby to achieve scheduling at the input side by an inter-line scheduler. An output buffer section assembles a variable-length packet from fixed-length packets that have been obtained by switching at a switch section in an output buffer section. A QoS control is performed based on a packet length.

摘要翻译： 为了在小规模硬件中高速实现可变长度分组的QoS控制，丢弃控制和组播控制，分组分配器将可变长度分组分成固定长度分组，并且输入缓冲部分存储分割的固定长度 数据包通过输出行和QoS类进入队列。 大量的QoS等级被映射到只有两种类型，包括保证分配的带宽的保证带宽等级，以及为其分配剩余带宽的最佳努力类，从而通过一个inter 线程调度器 输出缓冲器部分通过在输出缓冲器部分中的切换部分处切换而获得的固定长度分组组装可变长度分组。 基于分组长度执行QoS控制。

公开(公告)号：US06963577B1

公开(公告)日：2005-11-08

申请号：US09643566

申请日：2000-08-22

申请人： Hiroshi Tomonaga ,  Naoki Matuoka ,  Kenichi Kawarai ,  Tsuguo Kato

发明人： Hiroshi Tomonaga ,  Naoki Matuoka ,  Kenichi Kawarai ,  Tsuguo Kato

IPC分类号： H04L12/18 ,  H04L12/28 ,  H04L12/775 ,  H04L12/863 ,  H04L12/879 ,  H04L12/933 ,  H04L12/937 ,  H04L12/945

CPC分类号： H04L47/24 ,  H04L12/5601 ,  H04L49/106 ,  H04L49/90 ,  H04L49/901 ,  H04L2012/5679 ,  H04L2012/5681 ,  H04L2012/5683

摘要： A packet switch includes an input buffer memory unit having a logic queue corresponding to an output line, a control module for a first pointer indicating a scheduling start input line, a control module for a second pointer indicating a scheduling start output line of scheduling target outlines, a request management control module for retaining transmission request data about a desired output line, a scheduling processing module for starting a retrieval from within plural pieces of transmission request data from the output line indicated by the second pointer, and selecting an output line that is not ensured by other input lines, a packet buffer memory unit for temporarily storing a plurality of fixed-length packets and sequentially outputting the fixed-length packets, a switch unit for switching the fixed-length packets outputted from the packet buffer memory unit, and an address management unit for segmenting an address of the packet buffer memory unit into fixed-length blocks for a plurality of packets, and managing the address on a block basis. With this construction, the memory address is managed on the block basis, and a memory capacity can be reduced by giving an intra-block individual address per queue when in writing or reading.

摘要翻译： 分组交换机包括具有对应于输出线的逻辑队列的输入缓冲存储器单元，用于指示调度开始输入线的第一指针的控制模块，用于指示调度目标轮廓的调度开始输出行的第二指针的控制模块 ，用于保存关于期望输出线的发送请求数据的请求管理控制模块，用于从由第二指示器指示的输出线从多条发送请求数据中开始检索的调度处理模块，以及选择输出线 由其他输入线路不能保证，用于暂时存储多个固定长度分组并顺序地输出固定长度分组的分组缓冲存储器单元，用于切换从分组缓冲存储器单元输出的固定长度分组的切换单元，以及 地址管理单元，用于将分组缓冲存储器单元的地址分段成为a的固定长度块 多个分组，并且以块为基础管理地址。 利用这种结构，以块为基础管理存储器地址，并且可以通过在写入或读取时给出每个队列的块内单独地址来减小存储器容量。

公开(公告)号：US06920145B2

公开(公告)日：2005-07-19

申请号：US09759181

申请日：2001-01-12

申请人： Naoki Matsuoka ,  Hiroshi Tomonaga ,  Kenichi Kawarai

发明人： Naoki Matsuoka ,  Hiroshi Tomonaga ,  Kenichi Kawarai

IPC分类号： H04L12/931 ,  H04L12/937 ,  H04L12/56

CPC分类号： H04L49/608 ,  H04L49/205 ,  H04L49/254 ,  H04L49/30 ,  H04L49/3063 ,  H04L49/503 ,  H04L49/508 ,  H04L2012/5679

摘要： A packet switch device having a plurality of input buffers; a packet switch; a plurality of schedulers, having a pipeline scheduling process module wherein a plurality of time units corresponding to the number of output lines is spent in scheduled sending process of the fixed length packets from the input buffer, and wherein the scheduled sending process is executed in a number of processes, in parallel, the number of processes corresponding to the number of the input lines, having a sending status management module wherein sending status of the fixed length packets which constitute one frame is managed for each of the input lines, and provided corresponding to any of the output lines; and at least one result notification module for notifying the input buffer of result information from the scheduled sending process performed by each of the plurality of schedulers. Further, in the scheduled sending process executed in a number of processes, in parallel, the device does not select the input line sending the fixed length packets corresponding to the same frame, and, after determining a selection, the device maintains the selection of the same input line until the completion of sending the fixed length packets corresponding to the same frame.

摘要翻译： 一种具有多个输入缓冲器的分组交换设备; 分组交换机 多个调度器，其具有流水线调度处理模块，其中与输出线数相对应的多个时间单元在来自输入缓冲器的固定长度分组的调度发送过程中被消耗，并且其中调度发送过程以 并行处理对应于输入线数量的处理次数，具有发送状态管理模块，其中为每个输入行管理构成一帧的固定长度分组的发送状态，并且提供相应的 到任何输出线; 以及至少一个结果通知模块，用于从所述多个调度器中的每个调度器执行的所调度的发送处理通知结果信息的输入缓冲器。 此外，在多个处理中执行的调度发送处理中，并行地，设备不选择发送对应于同一帧的固定长度分组的输入行，并且在确定选择之后，设备保持对 相同的输入行直到完成发送对应于同一帧的固定长度数据包。

公开(公告)号：US06687225B1

公开(公告)日：2004-02-03

申请号：US09421465

申请日：1999-10-19

申请人： Kenichi Kawarai ,  Hiroshi Tomonaga ,  Naoki Matsuoka ,  Naotoshi Watanabe ,  Yasuhiro Ooba ,  Hichiro Hayami

发明人： Kenichi Kawarai ,  Hiroshi Tomonaga ,  Naoki Matsuoka ,  Naotoshi Watanabe ,  Yasuhiro Ooba ,  Hichiro Hayami

IPC分类号： H04L1256

CPC分类号： H04Q11/0478 ,  H04L12/5601 ,  H04L12/5602 ,  H04L2012/5625 ,  H04L2012/5632 ,  H04L2012/5651 ,  H04L2012/568

摘要： The invention relates to a bandwidth control apparatus in ATM equipment, for inserting management cells such as OAM cells, the control apparatus being configured to secure a bandwidth for the insertion of a management cell such as an OAM cell when the need arises, while guaranteeing the service quality of user cells, thereby making effective use of network resources for a best effort service such as ABR or UBR. The bandwidth control apparatus comprises a cell insertion block 1-10 for inserting a management cell such as an OAM cell and a shaping block 1-20 for performing user cell shaping, wherein the cell insertion block 1-10 issues an empty cell request when a cell insertion request occurs, the shaping block 1-20, upon receiving the empty cell insertion request, inserts an empty cell in a user cell stream being output from a shaping buffer 1-22, and the cell insertion block 1-10 writes a management cell such as an OAM cell over the empty cell inserted on a cell highway 1-30, thus sending the management cell out on the cell highway 1-30.

摘要翻译： 本发明涉及一种ATM设备中的带宽控制装置，用于插入诸如OAM小区的管理小区，该控制装置被配置为在需要时保证用于插入诸如OAM小区之类的管理小区的带宽，同时保证 用户单元的服务质量，从而有效利用网络资源实现最佳服务，如ABR或UBR。 带宽控制装置包括用于插入诸如OAM小区的管理小区的小区插入块1-10和用于进行用户小区整形的整形块1-20，其中，当小区插入块1-10发出空单元请求时， 单元插入请求发生时，整形块1-20在接收到空单元插入请求时，将其从一个整形缓冲器1-22输出的用户单元流中插入一个空单元，并且单元插入块1-10写入管理 小区，例如插入单元高速公路1-30上的空单元上的OAM单元，从而将单元高速公路1-30上的管理单元发送出去。

公开(公告)号：US08027262B2

公开(公告)日：2011-09-27

申请号：US11050152

申请日：2005-02-03

申请人： Kenichi Kawarai ,  Hiroyuki Kaneko ,  Kazuyuki Tajima ,  Kou Takatori

发明人： Kenichi Kawarai ,  Hiroyuki Kaneko ,  Kazuyuki Tajima ,  Kou Takatori

IPC分类号： H04J3/14

CPC分类号： H04L45/26 ,  H04L12/4641 ,  H04L45/02

摘要： An arbitrary node that belongs to a virtual LAN sends a request packet including a count value indicating the number of communication hops across nodes to each of its adjacent nodes that belong to the virtual LAN and are adjacent. Upon receiving the request packet, each of the adjacent nodes sends the request packet in which the count value is incremented or decremented to each of its adjacent nodes that belong to the virtual LAN and are adjacent to the node, excluding a sender of the request packet received, and sends a reply packet including the sender's address, an address of the node that is a replying node, and the count value to a given return destination. The return destination collects reply packets sent thereto and keeps track of the topology of the nodes constituting the virtual LAN from information contained in the reply packets.

摘要翻译： 属于虚拟LAN的任意节点将包含指示跨越节点的通信跳数的计数值的请求分组发送给属于虚拟LAN并且相邻的每个相邻节点。 在接收到请求分组时，每个相邻节点发送请求分组，其中计数值递增或递减到属于虚拟LAN的每个相邻节点，并且与节点相邻，不包括请求分组的发送者 接收并发送包括发送方地址，作为应答节点的节点的地址和计数值的应答分组到给定的返回目的地。 返回目的地收集发送到其中的应答分组，并且从包含在应答分组中的信息中跟踪构成虚拟LAN的节点的拓扑。