Loop test system in an integrated circuit
    1.
    发明授权
    Loop test system in an integrated circuit 失效
    集成电路中的环路测试系统

    公开(公告)号:US5239536A

    公开(公告)日:1993-08-24

    申请号:US671614

    申请日:1991-03-19

    CPC分类号: H04J3/14

    摘要: In the transmission data test mode of the integrated circuit, the user sets test transmission data as transmission data and supplies a transmission data test command to a returning unit, whereby the test transmission data output from the transmission unit is returned by the returning unit and received by the reception unit. In that case, a format converting unit receives the test transmission data in the data format of the transmission data. Then, by comparing the test transmission data and data received by the reception unit, the user can carry out a transmission data test. In the reception data test mode of the integrated circuit, the user sets test reception data, designates a reception timing and supplies a reception data test command to a test reception data input unit, whereby the test reception data is received by the reception unit via the test reception data input unit. Then, by comparing the test reception data and data received by the reception unit and corresponding to the designated reception timing, the user can perform a reception data test.

    摘要翻译: 在集成电路的发送数据测试模式中,用户将测试发送数据设置为发送数据,并将发送数据测试命令提供给返回单元,由此,从发送单元输出的测试发送数据由返回单元返回并接收 由接待单位。 在这种情况下,格式转换单元以发送数据的数据格式接收测试发送数据。 然后,通过比较测试发送数据和接收单元接收的数据,用户可以进行发送数据测试。 在集成电路的接收数据测试模式中,用户设置测试接收数据,指定接收定时,并将接收数据测试命令提供给测试接收数据输入单元,由此接收单元经由 测试接收数据输入单元。 然后,通过比较测试接收数据和由接收单元接收的数据并与指定的接收定时相对应,用户可以进行接收数据测试。

    Data transfer method performed in a data processor provided in a
switching system
    2.
    发明授权
    Data transfer method performed in a data processor provided in a switching system 失效
    在交换系统中提供的数据处理器中执行的数据传输方法

    公开(公告)号:US5271009A

    公开(公告)日:1993-12-14

    申请号:US655054

    申请日:1991-02-14

    CPC分类号: H04L29/06

    摘要: A packet data and a header added to a head of the packet data for specifying a transfer condition of the packet data are divided together to data blocks (DBs) each having a designated data length, consisting of an initial DB including the header and an initial part of the packet data, intermediate DBs each including an intermediate part of the packet data and a last DB including a last part of the packet data, so as to be transferred to a data transfer destination in a data processor of a switching system in accordance with write commands for the initial, intermediate and last DBs respectively, and a read command for asking whether the DBs are correctly transferred is sent to the data transfer destination once, after the DBs are transferred. When the DBs are transferred, the packet data is restored at the data transfer destination only by synthesizing the transferred DBs and removing the header.

    摘要翻译: 分组数据和添加到用于指定分组数据的传送条件的分组数据的头部的分组数据和标题被分割为每个具有指定数据长度的数据块(DB),其由包括报头的初始DB和初始 分组数据的一部分,每个包括分组数据的中间部分的中间DB和包括分组数据的最后部分的最后一个DB,以便根据切换系统的数据处理器被传送到数据传送目的地 分别用于初始,中间和最后一个DB的写入命令,以及一个用于询问DB是否被正确传输的读取命令在传输DB之后被发送到数据传输目的地一次。 当DB被传送时,仅通过合成所传送的DB并且去除标题来在数据传送目的地恢复分组数据。

    Subscriber line control apparatus to concurrently detect change in line
state for subscriber lines and determine validity of timer device
    4.
    发明授权
    Subscriber line control apparatus to concurrently detect change in line state for subscriber lines and determine validity of timer device 失效
    用户线路控制装置同时检测用户线路的线路状态变化并确定定时器设备的有效性

    公开(公告)号:US5577114A

    公开(公告)日:1996-11-19

    申请号:US434122

    申请日:1995-05-02

    CPC分类号: H04M3/2272 H04Q11/0407

    摘要: A subscriber line control device utilizes a scan input table and a last look table. The scan input table stores respective current line states of a plurality of analog subscriber lines. The last look table stores respective preceding line states of the plurality of analog subscriber lines and information for validating or invalidating a timer device. A valid timer device corresponds to when a monitoring process is required. The scan input table is compared with the last look table at every predetermined cycle. When they do not match, it is judged whether the line state has changed or if the timer device is validated. Based on the judging result, an analog subscriber line control is performed according to an instruction specified by a call processing unit. The analog subscriber control is any of a call origination monitor, a dial pulse monitor, and an on-hook and off-hook (HIT) monitor.

    摘要翻译: 用户线路控制装置利用扫描输入表和最后一个表。 扫描输入表存储多个模拟用户线的各自的当前线状态。 最后一个查看表存储多个模拟用户线的各自的前一行状态和用于验证或使定时装置无效的信息。 有效的定时器设备对应于何时需要监视进程。 将扫描输入表与每个预定周期的最后一个表进行比较。 当它们不匹配时,判断线路状态是否改变,或者定时器设备是否被验证。 根据判断结果,根据由呼叫处理单元指定的指令进行模拟用户线路控制。 模拟用户控制是呼叫发起监视器,拨号脉冲监视器以及挂机和摘机(HIT)监视器中的任何一个。

    Data transfer system including exchange
    5.
    发明授权
    Data transfer system including exchange 失效
    数据传输系统包括交换

    公开(公告)号:US5553066A

    公开(公告)日:1996-09-03

    申请号:US307109

    申请日:1994-09-16

    摘要: A data transfer system including an exchange, wherein the exchange transfers data by sharing a plurality of channels by a time division multiplex mode. In this case, the exchange transfers the data by variably allocating respective time slots to be occupied by the respective channels. That is, it is possible to allot any line speed to any channel and therefore possible to mix signals with different data transfer speeds in the frames. This results in an exchange network with a high degree of freedom of transfer for the subscriber terminal equipment.

    摘要翻译: 一种包括交换机的数据传输系统,其中所述交换机通过以时分复用模式共享多个信道来传送数据。 在这种情况下,交换机通过可变地分配要由相应信道占用的各个时隙来传送数据。 也就是说,可以将任何线路速度分配给任何通道,因此可以将不同数据传输速度的信号混合在帧中。 这导致用户终端设备具有高传输自由度的交换网络。

    Group III nitride compound semiconductor laser
    7.
    发明授权
    Group III nitride compound semiconductor laser 有权
    III族氮化物化合物半导体激光器

    公开(公告)号:US06801559B2

    公开(公告)日:2004-10-05

    申请号:US10383229

    申请日:2003-03-07

    IPC分类号: H01S319

    摘要: A semiconductor laser comprises a sapphire substrate, an AlN buffer layer, Si-doped GaN n-layer, Si-doped Al0.1Ga0.9N n-cladding layer, Si-doped GaN n-guide layer, an active layer having multiple quantum well (MQW) structure in which about 35 Å in thickness of GaN barrier layer 62 and about 35 Å in thickness of Ga0.95In0.55N well layer 61 are laminated alternately, Mg-doped GaN p-guide layer, Mg-doped Al0.25Ga0.75N p-layer, Mg-doped Al0.1Ga0.9N p-cladding layer, and Mg-doped GaN p-contact layer are formed successively thereon. A ridged hole injection part B which contacts to a ridged laser cavity part A is formed to have the same width as the width w of an Ni electrode. Because the p-layer has a larger aluminum composition, etching rate becomes smaller and that can prevent from damaging the p-guide layer in this etching process.

    摘要翻译: 半导体激光器包括蓝宝石衬底,AlN缓冲层,Si掺杂GaN n层,Si掺杂的Al 0.1 Ga 0.9 N n包层,Si掺杂的GaN n引导层,具有多个量子阱的有源层 (MQW)结构,其中GaN阻挡层62的厚度约为35,Ga0.95In0.55N阱层61的厚度约为35,Mg掺杂的GaN引导层,Mg掺杂的Al0.25Ga0 在其上依次形成了.75N p层,Mg掺杂的Al 0.1 Ga 0.9 N p包覆层和掺杂Mg的GaN p接触层。 与脊状激光腔部A接触的脊状空穴注入部B形成为与Ni电极的宽度w相同的宽度。 因为p层具有较大的铝组成,所以蚀刻速率变小,并且可以防止在该蚀刻工艺中损坏p导向层。

    ATM node and routing data registering apparatus
    9.
    发明授权
    ATM node and routing data registering apparatus 失效
    ATM节点和路由数据登记装置

    公开(公告)号:US5805592A

    公开(公告)日:1998-09-08

    申请号:US624941

    申请日:1996-03-22

    申请人: Takashi Hatano

    发明人: Takashi Hatano

    CPC分类号: H04L49/309 H04Q11/0478

    摘要: A CPU sets one of first and second memories as an "active system memory" and the other as a "standby system memory". Data about a combination of the VPI/VCI and TAG data is registered in and deleted from only the memory set as the "active system memory". The CPU, only when a null entry exists in a position satisfying a VPI/VCI increasing sequence with an increased address value, registers this null entry in the active system memory with data about new combination of the VPI/VCI and the TAG data. Whereas if there is no such null entry, the CPU reads the data about all the combinations of the VPI/VCI and the TAG data which are registered in the active system memory, re-sorts the read data and the data about the new combinations in the VPI/VCI increasing sequence and write the data from the head address in the standby system memory in a sorting sequence. The CPU, when finishing this writing process, resets the memory so far working as the standby system to an active system memory and the memory so far working as the active system to a standby system memory.

    摘要翻译: CPU将第一和第二存储器之一设置为“活动系统存储器”,将另一个设置为“备用系统存储器”。 关于VPI / VCI和TAG数据的组合的数据被登记在仅作为“活动系统存储器”的存储器中并从其中删除。 CPU只有当满足具有增加的地址值的VPI / VCI增加序列的位置中存在空条目时,才会向活动系统存储器中注册有关VPI / VCI和TAG数据的新组合的数据。 而如果没有这样的空条目,则CPU读取关于在活动系统存储器中注册的VPI / VCI和TAG数据的所有组合的数据,将读取的数据和关于新组合的数据重新排序 VPI / VCI增加序列,并以排序顺序从备用系统存储器中的头地址写入数据。 CPU在完成此写入过程时,将到目前为止的内存重置为备用系统到活动系统内存,并将存储器作为当前系统工作到备用系统内存。