公开(公告)号：US20120084526A1

公开(公告)日：2012-04-05

申请号：US13224710

申请日：2011-09-02

申请人： Masahiro ISE ,  Michiyo Garbe ,  Jin Abe

发明人： Masahiro ISE ,  Michiyo Garbe ,  Jin Abe

IPC分类号： G06F12/02 ,  G06F12/14

CPC分类号： G11C16/16 ,  G06F12/0246 ,  G06F2212/7204 ,  G06F2212/7205 ,  G11C16/30

摘要： An apparatus includes a nonvolatile memory, an interface that at least receives an erase command of the nonvolatile memory, a first controller that controls the nonvolatile memory to execute data erasing on the basis of the erase command output from the interface, an external input unit which is installed independently of the interface, a second controller that controls the nonvolatile memory to execute data erasing on the basis of an erase instruction signal output from the external input unit, and a change-over circuit that switches between connection of the first controller with the nonvolatile memory and connection of the second controller with the nonvolatile memory, wherein the second controller controls the nonvolatile memory to execute data erasing on the basis of the erase instruction when the connection of the second controller with the nonvolatile memory is established by the change-over circuit.

摘要翻译： 一种装置，包括非易失性存储器，至少接收非易失性存储器的擦除命令的接口，第一控制器，其基于从接口输出的擦除命令来控制非易失性存储器执行数据擦除;外部输入单元， 独立于接口安装的第二控制器，控制非易失性存储器以基于从外部输入单元输出的擦除指令信号执行数据擦除的第二控制器，以及转换电路，其在第一控制器与第二控制器的连接之间切换 非易失性存储器和第二控制器与非易失性存储器的连接，其中当通过转换建立第二控制器与非易失性存储器的连接时，第二控制器基于擦除指令控制非易失性存储器执行数据擦除 电路。

公开(公告)号：US06333932B1

公开(公告)日：2001-12-25

申请号：US08518110

申请日：1995-08-21

申请人： Yasusi Kobayasi ,  Yoshihiro Watanabe ,  Hiroshi Nishida ,  Masami Murayama ,  Naoyuki Izawa ,  Yasuhiro Aso ,  Yoshihiro Uchida ,  Hiromi Yamanaka ,  Jin Abe ,  Yoshihisa Tsuruta ,  Yoshiharu Kato ,  Satoshi Kakuma ,  Shiro Uriu ,  Noriko Samejima ,  Eiji Ishioka ,  Shigeru Sekine ,  Yoshiyuki Karakawa ,  Atsushi Kagawa ,  Mikio Nakayama ,  Miyuki Kawataka ,  Satoshi Esaka ,  Nobuyuki Tsutsui ,  Fumio Hirase ,  Atsuko Suzuki ,  Shouji Kohira ,  Kenichi Okabe ,  Takashi Hatano ,  Yasuhiro Nishikawa ,  Jun Itoh ,  Shinichi Araya

发明人： Yasusi Kobayasi ,  Yoshihiro Watanabe ,  Hiroshi Nishida ,  Masami Murayama ,  Naoyuki Izawa ,  Yasuhiro Aso ,  Yoshihiro Uchida ,  Hiromi Yamanaka ,  Jin Abe ,  Yoshihisa Tsuruta ,  Yoshiharu Kato ,  Satoshi Kakuma ,  Shiro Uriu ,  Noriko Samejima ,  Eiji Ishioka ,  Shigeru Sekine ,  Yoshiyuki Karakawa ,  Atsushi Kagawa ,  Mikio Nakayama ,  Miyuki Kawataka ,  Satoshi Esaka ,  Nobuyuki Tsutsui ,  Fumio Hirase ,  Atsuko Suzuki ,  Shouji Kohira ,  Kenichi Okabe ,  Takashi Hatano ,  Yasuhiro Nishikawa ,  Jun Itoh ,  Shinichi Araya

IPC分类号： H04Q1104

CPC分类号： H04L5/16 ,  H04L2012/5628 ,  H04L2012/5645 ,  H04L2012/5652 ,  H04Q11/0478

摘要： The quality and performance of the connectionless communications system are improved. When a BOM is received, the destination address DA of the L3-PDU stored in the payload of the BOM is retrieved, and the tag information is obtained from the DA (S11). The output message identifier MID is reserved (S12), and the tag information and output MID are assigned to the BOM (S13). Then, the tag information and output MID are written to the table. When a COM is received, the tag information and output MID are retrieved using the MID of the COM as a key, and the information is provided for the COM (S31 and S32). When an EOM is received, the tag information and output MID are retrieved using the MID of the EOM as a key, and the information is provided for the EOM (S41 and S42). Then, the output MID is released (S43).

摘要翻译： 无连接通信系统的质量和性能得到提高。 当接收到BOM时，检索存储在BOM的有效载荷中的L3-PDU的目的地地址DA，并从DA获得标签信息（S11）。 输出消息标识符MID被保留（S12），标签信息和输出MID被分配给BOM（S13）。 然后，将标签信息和输出MID写入表中。 当接收到COM时，使用COM的MID作为密钥检索标签信息和输出MID，并为COM提供信息（S31和S32）。 当接收到EOM时，使用EOM的MID作为密钥检索标签信息和输出MID，并且为EOM提供信息（S41和S42）。 然后，释放输出MID（S43）。

公开(公告)号：US5974458A

公开(公告)日：1999-10-26

申请号：US637090

申请日：1996-04-24

申请人： Jin Abe ,  Tetsuya Nishi

发明人： Jin Abe ,  Tetsuya Nishi

IPC分类号： H04L12/14 ,  H04L12/56 ,  H04L29/06 ,  H04Q11/04 ,  G06F15/163

CPC分类号： H04L12/1403 ,  H04L12/14 ,  H04L69/04 ,  H04Q11/0478 ,  H04L2012/5636

摘要： Source data is stored in a source data storage unit and a comparing device compares source data with destination data stored in a destination data storage unit. A destination address compressing unit compresses destination address information, and other accounting parameters are output with some delay. An accumulating device accumulates information from the destination address compressing unit as an address. A source address compressing unit compresses or delays information from an accumulating unit, and then outputs information. A source address carrier compressing unit compresses or delays information from the source address compressing unit, and then outputs information. A destination address source address carrier re-compressing unit compresses or delays compressed information from the source address carrier compressing unit, and then outputs information. A period abnormality detecting circuit in an accounting unit validates transfer data and prevents a wrong accounting process from being performed.

摘要翻译： 源数据存储在源数据存储单元中，比较装置将源数据与存储在目的地数据存储单元中的目的地数据进行比较。 目的地地址压缩单元压缩目的地址信息，其他计费参数输出一些延迟。 累积装置将来自目的地地址压缩单元的信息作为地址进行累积。 源地址压缩单元压缩或延迟来自累积单元的信息，然后输出信息。 源地址载体压缩单元压缩或者延迟来自源地址压缩单元的信息，然后输出信息。 目的地址源地址载波再压缩单元压缩或者延迟来自源地址载波压缩单元的压缩信息，然后输出信息。 会计单元中的周期异常检测电路验证传输数据，防止执行错误的计费处理。

公开(公告)号：US08856474B2

公开(公告)日：2014-10-07

申请号：US13224710

申请日：2011-09-02

申请人： Masahiro Ise ,  Michiyo Garbe ,  Jin Abe

发明人： Masahiro Ise ,  Michiyo Garbe ,  Jin Abe

IPC分类号： G06F12/00 ,  G11C16/30 ,  G11C16/16 ,  G06F12/02

CPC分类号： G11C16/16 ,  G06F12/0246 ,  G06F2212/7204 ,  G06F2212/7205 ,  G11C16/30

摘要： An apparatus includes a nonvolatile memory, an interface that at least receives an erase command of the nonvolatile memory, a first controller that controls the nonvolatile memory to execute data erasing on the basis of the erase command output from the interface, an external input unit which is installed independently of the interface, a second controller that controls the nonvolatile memory to execute data erasing on the basis of an erase instruction signal output from the external input unit, and a change-over circuit that switches between connection of the first controller with the nonvolatile memory and connection of the second controller with the nonvolatile memory, wherein the second controller controls the nonvolatile memory to execute data erasing on the basis of the erase instruction when the connection of the second controller with the nonvolatile memory is established by the change-over circuit.

摘要翻译： 一种装置，包括非易失性存储器，至少接收非易失性存储器的擦除命令的接口，第一控制器，其基于从接口输出的擦除命令来控制非易失性存储器执行数据擦除;外部输入单元， 独立于接口安装的第二控制器，控制非易失性存储器以基于从外部输入单元输出的擦除指令信号执行数据擦除的第二控制器，以及转换电路，其在第一控制器与第二控制器的连接之间切换 非易失性存储器和第二控制器与非易失性存储器的连接，其中当通过转换建立第二控制器与非易失性存储器的连接时，第二控制器基于擦除指令控制非易失性存储器执行数据擦除 电路。

公开(公告)号：US08027221B2

公开(公告)日：2011-09-27

申请号：US12560224

申请日：2009-09-15

申请人： Jin Abe ,  Osamu Ishibashi ,  Yoshinori Mesaki

发明人： Jin Abe ,  Osamu Ishibashi ,  Yoshinori Mesaki

IPC分类号： G11C8/00

CPC分类号： G11C5/143 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/4076

摘要： A memory device that can include a power-supply voltage detector that detects power-supply voltage values and that outputs a detection result indicating which power-supply voltage value is detected; a data-rate setter that sets data rates corresponding to the detection result of the power-supply voltage detector, in synchronization with a rising edge or falling edge of a clock signal; and a memory cell array that performs reading/writing at the data rates set by the data-rate setter.

摘要翻译： 一种存储器件，其可以包括电源电压检测器，其检测电源电压值并输出检测结果，该检测结果指示检测到哪个电源电压值; 与时钟信号的上升沿或下降沿同步地设定与电源电压检测器的检测结果相对应的数据速率的数据速率设定器; 以及以由数据速率设定器设定的数据速率进行读/写的存储单元阵列。

公开(公告)号：US20100067313A1

公开(公告)日：2010-03-18

申请号：US12560224

申请日：2009-09-15

申请人： Jin Abe ,  Osamu Ishibashi ,  Yoshinori Mesaki

发明人： Jin Abe ,  Osamu Ishibashi ,  Yoshinori Mesaki

IPC分类号： G11C7/00 ,  G11C5/14 ,  G11C8/18

CPC分类号： G11C5/143 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/4076

摘要： A memory device that can include a power-supply voltage detector that detects power-supply voltage values and that outputs a detection result indicating which power-supply voltage value is detected; a data-rate setter that sets data rates corresponding to the detection result of the power-supply voltage detector, in synchronization with a rising edge or falling edge of a clock signal; and a memory cell array that performs reading/writing at the data rates set by the data-rate setter.

摘要翻译： 一种存储器件，其可以包括电源电压检测器，其检测电源电压值并输出检测结果，该检测结果指示检测到哪个电源电压值; 与时钟信号的上升沿或下降沿同步地设定与电源电压检测器的检测结果相对应的数据速率的数据速率设定器; 以及以由数据速率设定器设定的数据速率进行读/写的存储单元阵列。

公开(公告)号：US07434086B2

公开(公告)日：2008-10-07

申请号：US11023011

申请日：2004-12-28

申请人： Jin Abe ,  Hirokazu Fukui ,  Kazuhiro Kaneko

发明人： Jin Abe ,  Hirokazu Fukui ,  Kazuhiro Kaneko

IPC分类号： G06F11/00

CPC分类号： G06F11/20 ,  G06F11/142

摘要： This invention relates to a functional device such as an FPGA carrying out a necessary function by programming, and provides a functional device, a function maintaining method and a function maintaining program which can maintain a function continuously. A plurality of function parts (FPGAs) is provided, and a function is maintained by switching from a function part, in which a failure is occurring, to a function part under stand-by. The plurality of function parts, a failure detection part (failure detection circuits) and a switching part (switching circuits) are provided, and a function part under operation and a function part under stand-by a reset. That is, the function part in which the failure is occurring is made into a stand-by state, and the function part which is under stand-by is made to operate. Therefore, the continuous function can be maintained without stopping the operation of a system due to the failure occurring in the function part, and the reliability of the system is heightened by the maintenance of the function.

摘要翻译： 本发明涉及通过编程实现必要功能的FPGA等功能装置，提供可以连续地保持功能的功能装置，功能维护方法和功能维护程序。 提供多个功能部件（FPGA），并且通过从发生故障的功能部件切换到待机功能部件来维护功能。 提供多个功能部件，故障检测部件（故障检测电路）和开关部件（开关电路），以及正在运行的功能部件和备用复位功能部件。 也就是说，发生故障的功能部件成为待机状态，使待机的功能部件工作。 因此，由于功能部件发生故障，可以维持连续功能而不停止系统的运转，并且通过维护功能来提高系统的可靠性。

公开(公告)号：US20060036912A1

公开(公告)日：2006-02-16

申请号：US11023011

申请日：2004-12-28

申请人： Jin Abe ,  Hirokazu Fukui ,  Kazuhiro Kaneko

发明人： Jin Abe ,  Hirokazu Fukui ,  Kazuhiro Kaneko

IPC分类号： G06F11/00

CPC分类号： G06F11/20 ,  G06F11/142

摘要： This invention relates to a functional device such as an FPGA carrying out a necessary function by programming, and provides a functional device, a function maintaining method and a function maintaining program which can maintain a function continuously. A plurality of function parts (FPGAs) is provided, and a function is maintained by switching from a function part, in which a failure is occurring, to a function part under stand-by. The plurality of function parts, a failure detection part (failure detection circuits) and a switching part (switching circuits) are provided, and a function part under operation and a function part under stand-by a reset. That is, the function part in which the failure is occurring is made into a stand-by state, and the function part which is under stand-by is made to operate. Therefore, the continuous function can be maintained without stopping the operation of a system due to the failure occurring in the function part, and the reliability of the system is heightened by the maintenance of the function.

摘要翻译： 本发明涉及通过编程实现必要功能的FPGA等功能装置，提供可以连续地保持功能的功能装置，功能维护方法和功能维护程序。 提供多个功能部件（FPGA），并且通过从发生故障的功能部件切换到待机功能部件来维护功能。 提供多个功能部件，故障检测部件（故障检测电路）和开关部件（开关电路），以及正在运行的功能部件和备用复位功能部件。 也就是说，发生故障的功能部件成为待机状态，使待机的功能部件工作。 因此，由于功能部件发生故障，可以维持连续功能而不停止系统的运转，并且通过维护功能来提高系统的可靠性。

公开(公告)号：US08687454B2

公开(公告)日：2014-04-01

申请号：US13609650

申请日：2012-09-11

申请人： Jin Abe ,  Osamu Ishibashi ,  Masahiro Ise

发明人： Jin Abe ,  Osamu Ishibashi ,  Masahiro Ise

IPC分类号： G11C8/00

CPC分类号： G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C16/08 ,  G11C16/10

摘要： In a semiconductor storage apparatus, an internal address generation unit generates, when receiving successive first and second external addresses, from the second external address an internal address for selecting any of the memory cells connected to bit lines and word lines except the bit line and word line connected to a memory cell to be selected according to the first external address. When receiving the successive external addresses, a memory cell connected to the same bit line and word line is not continuously selected, and erroneous readout due to rewriting of a value of the memory cell in a non-selected state is suppressed.

摘要翻译： 在半导体存储装置中，当从第二外部地址接收连续的第一和第二外部地址时，内部地址生成单元产生用于选择与比特线和字之外的位线和字线连接的任何存储单元的内部地址 线路连接到根据第一外部地址选择的存储器单元。 当接收到连续的外部地址时，不连续选择连接到同一位线和字线的存储单元，并且抑制由于重写未选择状态的存储单元的值而导致的错误读出。

公开(公告)号：US20070230147A1

公开(公告)日：2007-10-04

申请号：US11589093

申请日：2006-10-30

申请人： Jin Abe

发明人： Jin Abe

IPC分类号： H05K7/12 ,  H05K7/10

CPC分类号： H05K1/0268 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0292 ,  H05K1/111 ,  H05K1/112 ,  H05K1/181 ,  Y02P70/611 ,  H01L2924/00012

摘要： A circuit board having a mount part onto which the electronic component is mounted includes a plurality of wiring patterns at least one of which is electrically connectible to one of a plurality of first terminals of an electronic component, the plurality of first terminals being hidden by the electronic component once the electronic component is mounted onto the mount part, a pair of second terminals that expose around a mount part, one of the pair of second terminals being one-by-one connected to each first terminal, the other of the pair of second terminals being connected to each wiring pattern, and a signal line that exposes around the mount part and electrically connects the pair of second terminals to each other.

摘要翻译： 具有安装有电子部件的安装部的电路基板包括多个布线图案，其中至少一个布线图形可电连接到电子部件的多个第一端子中的一个，多个第一端子被 电子部件一旦安装到安装部件上，则一对第二端子暴露在安装部分周围，一对第二端子中的一个连接到每个第一端子，另一个连接到每个第一端子 第二端子连接到每个布线图案，以及信号线，其暴露在安装部分周围并将一对第二端子彼此电连接。