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    Transistor structure with minimized parasitics and method of fabricating the same
    2.
    发明申请
    Transistor structure with minimized parasitics and method of fabricating the same 失效
    具有最小化寄生效应的晶体管结构及其制造方法

    公开(公告)号：US20050191911A1

    公开(公告)日：2005-09-01

    申请号：US10789282

    申请日：2004-02-27

    申请人： David Greenberg ,  Shwu-Jen Jeng

    发明人： David Greenberg ,  Shwu-Jen Jeng

    IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/423 ,  H01L29/72 ,  H01L29/73 ,  H01L29/732

    CPC分类号： H01L29/66287 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/42308 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

    摘要： A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.

    摘要翻译： 提供了具有最小化寄生效应的晶体管，其包括在本征发射极部分顶部具有凹入的非本征发射极部分的发射极; 包括与本征发射极部分电接触的本征基极部分的基极和与本征基极部分电接触并且通过一组发射极/基底间隔物与凹入的非本征发射极部分电隔离的非本征基极部分; 以及与本征基部电接触的集电体。 晶体管可以进一步包括具有完全硅化到发射极/基极间隔物的顶表面的外在基极。 另外，晶体管可以包括在晶体管的有效区域内的基极窗口。 还提供了形成上述晶体管的方法。

    ANTIMICROBIAL GAS IMPREGNATING DEVICES AND METHODS
    4.
    发明申请
    ANTIMICROBIAL GAS IMPREGNATING DEVICES AND METHODS 有权
    抗微生物气体注入装置和方法

    公开(公告)号：US20100268149A1

    公开(公告)日：2010-10-21

    申请号：US12825373

    申请日：2010-06-29

    申请人： Yossef AV-GAY ,  David Greenberg

    发明人： Yossef AV-GAY ,  David Greenberg

    IPC分类号： A61F11/00 ,  A61M37/00

    CPC分类号： A61F11/002 ,  A61K33/00 ,  A61L31/04 ,  A61L31/10 ,  A61L31/16 ,  A61L2300/114 ,  A61L2300/404 ,  A61L2300/45 ,  A61L2430/14 ,  A61M27/002

    摘要： A nitric oxide gas-releasing conduit configured for surgical implantation through a patient's tympanic membrane. The nitric oxide gas-releasing conduit comprises a gas-permeable cured resin material configured for releasably sequestering therein gas. The gas-permeable cured resin material is charged with nitric oxide gas. The nitric oxide gas-releasing conduit may be optionally coated with an antimicrobial gas-releasing composition. The gas-releasing coating composition may be configured to release nitric oxide.

    摘要翻译： 一氧化氮气体释放导管，其构造成用于通过患者的鼓膜进行手术植入。 一氧化氮气体释放导管包括构造成可释放地将其中的气体隔离的透气性固化树脂材料。 透气性固化树脂材料装有一氧化氮气体。 一氧化氮气体释放管道可任选地涂覆有抗微生物气体释放组合物。 气体释放涂料组合物可以被配置为释放一氧化氮。

    ANTIMICROBIAL GAS-RELEASING EAR DRAINAGE TUBES
    5.
    发明申请
    ANTIMICROBIAL GAS-RELEASING EAR DRAINAGE TUBES 有权
    抗菌气体释放排水管

    公开(公告)号：US20090131883A1

    公开(公告)日：2009-05-21

    申请号：US12234599

    申请日：2008-09-19

    申请人： Yossef Av-Gay ,  David Greenberg

    发明人： Yossef Av-Gay ,  David Greenberg

    IPC分类号： A61F11/00 ,  B05D5/00

    CPC分类号： A61F11/002 ,  A61K33/00 ,  A61L31/04 ,  A61L31/10 ,  A61L31/16 ,  A61L2300/114 ,  A61L2300/404 ,  A61L2300/45 ,  A61L2430/14 ,  A61M27/002

    摘要： A nitric oxide gas-releasing conduit configured for surgical implantation through a patient's tympanic membrane. The nitric oxide gas-releasing conduit comprises a gas-permeable cured resin material configured for releasably sequestering therein gas. The gas-permeable cured resin material is charged with nitric oxide gas. The nitric oxide gas-releasing conduit may be optionally coated with an antimicrobial gas-releasing composition. The gas-releasing coating composition may be configured to release nitric oxid.

    摘要翻译： 一氧化氮气体释放导管，其构造成用于通过患者的鼓膜进行手术植入。 一氧化氮气体释放导管包括构造成可释放地将其中的气体隔离的气体可渗透的固化树脂材料。 透气性固化树脂材料装有一氧化氮气体。 一氧化氮气体释放管道可任选地涂覆有抗微生物气体释放组合物。 气体释放涂料组合物可以被配置为释放一氧化氮。

    MULTI-LEVEL INTERCONNECTIONS FOR AN INTEGRATED CIRCUIT CHIP
    6.
    发明申请
    MULTI-LEVEL INTERCONNECTIONS FOR AN INTEGRATED CIRCUIT CHIP 有权
    集成电路芯片的多级互连

    公开(公告)号：US20060289994A1

    公开(公告)日：2006-12-28

    申请号：US11160463

    申请日：2005-06-24

    申请人： David Greenberg ,  John Pekarik ,  Jorg Scholvin

    发明人： David Greenberg ,  John Pekarik ,  Jorg Scholvin

    IPC分类号： H01L23/52

    CPC分类号： H01L23/528 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.

    摘要翻译： 用于集成电路芯片的多层金属化布局包括具有金属化布局连接的第一，第二和第三元件的晶体管。 该布局使包括电迁移在内的电流限制机制最小化，从而将第二触点的连接从芯片垂直定位，将金属化布局的平面和手指重叠到第一和第二元件，并形成多层金属化层的金字塔或楼梯以平滑对角线电流 流。

    STRUCTURE AND METHOD OF MAKING A FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRICALLY STRESSED CHANNEL REGION
    7.
    发明申请
    STRUCTURE AND METHOD OF MAKING A FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRICALLY STRESSED CHANNEL REGION 有权
    制造具有非对称应力通道区域的场效应晶体管的结构和方法

    公开(公告)号：US20060255415A1

    公开(公告)日：2006-11-16

    申请号：US10908448

    申请日：2005-05-12

    申请人： Gregory Freeman ,  Anil Chinthakindi ,  David Greenberg ,  Basanth Jagannathan ,  Marwan Khater ,  John Pekarik ,  Xudong Wang

    发明人： Gregory Freeman ,  Anil Chinthakindi ,  David Greenberg ,  Basanth Jagannathan ,  Marwan Khater ,  John Pekarik ,  Xudong Wang

    IPC分类号： H01L29/76

    CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7843

    摘要： A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.

    摘要翻译： 提供一种场效应晶体管，其包括其中设置有源极区，沟道区和漏极区的邻接单晶半导体区。 沟道区域具有与源极区域共同的边缘作为源极边缘，并且沟道区域还具有与作为漏极边缘的漏极区域共同的边缘。 栅极导体覆盖沟道区域。 场效应晶体管还包括将源极边缘和漏极边缘的另一个施加不大于第二幅度的应力的第一幅度的应力仅施加到源极边缘和漏极边缘中的一个的结构， 其中所述第二幅度具有从零到所述第一幅度的大约一半的值。 在特定实施例中，将应力以第一幅度施加到源极边缘，同时零或较小幅度应力施加到漏极边缘。 在另一个实施例中，将应力以第一幅度施加到漏极边缘，同时将零或较小的幅度应力施加到漏极边缘。

    STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR
    9.
    发明申请
    STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR 有权
    带有收集器的自对准双极晶体管的结构和方法

    公开(公告)号：US20050184359A1

    公开(公告)日：2005-08-25

    申请号：US10708340

    申请日：2004-02-25

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory Freeman ,  David Greenberg ,  Marwan Khater ,  William Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory Freeman ,  David Greenberg ,  Marwan Khater ,  William Tonti

    IPC分类号： H01L21/331 ,  H01L27/082 ,  H01L29/08 ,  H01L29/737

    CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

    摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.

    摘要翻译： 提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积 下表面。 双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。 在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。