公开(公告)号：US06990388B2

公开(公告)日：2006-01-24

申请号：US11020395

申请日：2004-12-27

申请人： Hiroyuki Akimori ,  Yasushi Ohyama ,  Hidetaka Nishimura ,  Shigeru Kobayashi

发明人： Hiroyuki Akimori ,  Yasushi Ohyama ,  Hidetaka Nishimura ,  Shigeru Kobayashi

IPC分类号： G06F19/00

CPC分类号： G06Q10/06 ,  G06Q50/04 ,  Y02P90/30

摘要： A mass-production transfer support system has a mass-production transfer source managing computer for managing information generated in a trial-production process of a semiconductor device and a mass-production transfer destination managing computer for managing a mass-production process of the semiconductor device. The mass-production transfer source managing computer comprises: quality/recipe information input accepting means; quality/recipe information sending means; apparatus-difference correction information input accepting means for accepting an input of apparatus-difference correction information for correcting a difference in the quality of the semiconductor device associated with an apparatus-difference between semiconductor manufacturing apparatuses; apparatus-difference correction information storing means; and apparatus-difference correction information providing means for storing the apparatus-difference correction information in a database accessible by the mass-production transfer destination managing computer.

摘要翻译： 批量生产转移支持系统具有用于管理在半导体器件的试生产过程中生成的信息的批量生产转移源管理计算机和用于管理半导体器件的批量生产过程的批量生产转移目的地管理计算机 。 批量生产转移源管理计算机包括：质量/食谱信息输入接收装置; 质量/配方信息发送装置; 装置差异校正信息输入接受装置，用于接受用于校正与半导体制造装置之间的装置差相关的半导体装置的质量差异的装置差校正信息的输入; 装置差校正信息存储装置; 以及装置差异校正信息提供装置，用于将装置差异校正信息存储在可由大规模生产转移目的地管理计算机访问的数据库中。

公开(公告)号：US20050143853A1

公开(公告)日：2005-06-30

申请号：US11020395

申请日：2004-12-27

申请人： Hiroyuki Akimori ,  Yasushi Ohyama ,  Hidetaka Nishimura ,  Shigeru Kobayashi

发明人： Hiroyuki Akimori ,  Yasushi Ohyama ,  Hidetaka Nishimura ,  Shigeru Kobayashi

IPC分类号： G06Q10/00 ,  G06Q50/00 ,  G06F19/00

CPC分类号： G06Q10/06 ,  G06Q50/04 ,  Y02P90/30

摘要： A mass-production transfer support system has a mass-production transfer source managing computer for managing information generated in a trial-production process of a semiconductor device and a mass-production transfer destination managing computer for managing a mass-production process of the semiconductor device. The mass-production transfer source managing computer comprises: quality/recipe information input accepting means; quality/recipe information sending means; apparatus-difference correction information input accepting means for accepting an input of apparatus-difference correction information for correcting a difference in the quality of the semiconductor device associated with an apparatus-difference between semiconductor manufacturing apparatuses; apparatus-difference correction information storing means; and apparatus-difference correction information providing means for storing the apparatus-difference correction information in a database accessible by the mass-production transfer destination managing computer.

摘要翻译： 批量生产转移支持系统具有用于管理在半导体器件的试生产过程中生成的信息的批量生产转移源管理计算机和用于管理半导体器件的批量生产过程的批量生产转移目的地管理计算机 。 批量生产转移源管理计算机包括：质量/食谱信息输入接收装置; 质量/配方信息发送装置; 装置差异校正信息输入接受装置，用于接受用于校正与半导体制造装置之间的装置差相关的半导体装置的质量差异的装置差校正信息的输入; 装置差校正信息存储装置; 以及装置差异校正信息提供装置，用于将装置差异校正信息存储在可由大规模生产转移目的地管理计算机访问的数据库中。

公开(公告)号：US06894334B2

公开(公告)日：2005-05-17

申请号：US10376329

申请日：2003-03-03

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/29 ,  H01L23/495 ,  H01L23/525 ,  H01L23/532 ,  H01L23/544 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0922 ,  H01L27/0928 ,  H01L27/10808 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤 通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤， 面具已被删除。

公开(公告)号：US06548847B2

公开(公告)日：2003-04-15

申请号：US09899921

申请日：2001-07-09

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： H01L2976

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0922 ,  H01L27/0928 ,  H01L27/10808 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤 通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤， 面具已被删除。

公开(公告)号：US06169324A

公开(公告)日：2001-01-02

申请号：US09413754

申请日：1999-10-06

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： H01L2144

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0922 ,  H01L27/0928 ,  H01L27/10808 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤 通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤， 面具已被删除。

公开(公告)号：US5780882A

公开(公告)日：1998-07-14

申请号：US456788

申请日：1995-06-01

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/29 ,  H01L23/495 ,  H01L23/525 ,  H01L23/532 ,  H01L23/544 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L27/0922 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0928 ,  H01L27/10808 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

公开(公告)号：US6127255A

公开(公告)日：2000-10-03

申请号：US943729

申请日：1997-10-03

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/29 ,  H01L23/495 ,  H01L23/525 ,  H01L23/532 ,  H01L23/544 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L21/4763 ,  H01L21/469

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L27/0922 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0928 ,  H01L27/10808 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由元件分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的有源区的主表面上形成MISFET。 所公开的方法包括在包括最上面布线的布线上形成绝缘膜，最上面的布线在相邻最上布线之间具有间隙。 绝缘膜包括在布线和相邻的最上布线之间的间隙中形成氧化硅膜，并且在氧化硅膜上形成氮化硅膜，通过等离子体化学气相沉积形成氮化硅膜。 氧化硅膜形成为具有至少相邻最上面布线之间的间隙的一半的厚度，其中氮化硅膜比氧化硅膜厚。

公开(公告)号：US5739589A

公开(公告)日：1998-04-14

申请号：US657194

申请日：1996-06-03

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/29 ,  H01L23/495 ,  H01L23/525 ,  H01L23/532 ,  H01L23/544 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L27/0922 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0928 ,  H01L27/10808 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤 通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤， 面具已被删除。

公开(公告)号：US5202275A

公开(公告)日：1993-04-13

申请号：US496330

申请日：1990-03-20

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/29 ,  H01L23/495 ,  H01L23/525 ,  H01L23/532 ,  H01L23/544 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L27/0922 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0928 ,  H01L27/10808 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤 通过不可氧化掩模的第一掩模和顺序地在所述衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区和非活性区域的全部表面部分中的方式，在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤， 面具已被删除。

公开(公告)号：US5811316A

公开(公告)日：1998-09-22

申请号：US460931

申请日：1995-06-05

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/29 ,  H01L23/495 ,  H01L23/525 ,  H01L23/532 ,  H01L23/544 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L21/28

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L27/0922 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0928 ,  H01L27/10808 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤 通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤， 面具已被删除。