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    Semiconductor device and method of manufacturing the same
    1.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US08242605B2

    公开(公告)日：2012-08-14

    申请号：US12795863

    申请日：2010-06-08

    申请人： Hiroyuki Arie ,  Nobuaki Umemura ,  Nobuyoshi Hattori ,  Nobuto Nakanishi ,  Kimio Hara ,  Kyoya Nitta ,  Makoto Ishikawa

    发明人： Hiroyuki Arie ,  Nobuaki Umemura ,  Nobuyoshi Hattori ,  Nobuto Nakanishi ,  Kimio Hara ,  Kyoya Nitta ,  Makoto Ishikawa

    IPC分类号： H01L23/48

    CPC分类号： H01L29/7835 ,  H01L21/02057 ,  H01L21/743 ,  H01L29/4175 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.

    摘要翻译： 在具有LDMOSFET的半导体器件中，源电极位于其后表面。 因此，为了降低顶表面的源极接触区域与后表面的源电极之间的电阻，提供了通过P型外延从上表面延伸到P +型衬底的多晶硅埋入式插塞 并用硼重掺杂。 在多晶硅埋塞塞周围的单晶硅区域发生位错，引起泄漏故障。 半导体器件具有延伸穿过具有不同杂质浓度的第一和第二半导体层之间的边界表面的硅基插塞。 至少插头的内部是多晶区域。 在多晶区域的表面中，位于与其相邻的上述边界面的两侧的部分各自被固相外延区域覆盖。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07245531B2

    公开(公告)日：2007-07-17

    申请号：US11198191

    申请日：2005-08-08

    申请人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

    发明人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

    IPC分类号： G11C11/34

    CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

    摘要： Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.

    摘要翻译： 存储单元以多个阵列形式布置。 选择沿X方向布置的存储单元的选择栅电极分别通过选择栅极线彼此连接。 存储器栅极电极分别由存储器栅极线连接。 分别连接到彼此相邻的存储单元的存储器栅极的存储栅极线通过其间的源极区域彼此不电连接。 每个选择栅极线具有在X方向上延伸的第一部分和其一端连接到第一部分并沿Y方向延伸的第二部分9b。 存储栅极线在其选择栅线的相应侧壁上形成有介于其间的绝缘膜。 存储栅极线具有接触部分，该接触部分在选择栅极线的第二部分上方在X方向上延伸到元件隔离区域上方，并且通过塞子连接到其对应的布线，所述插头埋设形成在触点上的接触孔 部分。

    Semiconductor device
    7.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060028868A1

    公开(公告)日：2006-02-09

    申请号：US11198191

    申请日：2005-08-08

    申请人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

    发明人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

    IPC分类号： G11C11/34 ,  G11C5/06

    CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

    摘要： Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.

    摘要翻译： 存储单元以多个阵列形式布置。 选择沿X方向布置的存储单元的选择栅电极分别通过选择栅极线彼此连接。 存储器栅极电极分别由存储器栅极线连接。 分别连接到彼此相邻的存储单元的存储器栅极的存储栅极线通过其间的源极区域彼此不电连接。 每个选择栅极线具有在X方向上延伸的第一部分和其一端连接到第一部分并沿Y方向延伸的第二部分9b。 存储栅极线在其选择栅线的相应侧壁上形成有介于其间的绝缘膜。 存储栅极线具有接触部分，该接触部分在选择栅极线的第二部分上方在X方向上延伸到元件隔离区域上方，并且通过塞子连接到其对应的布线，所述插头埋设形成在触点上的接触孔 部分。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US08344454B2

    公开(公告)日：2013-01-01

    申请号：US13048926

    申请日：2011-03-16

    申请人： Kyoya Nitta ,  Yutaka Hoshino

    发明人： Kyoya Nitta ,  Yutaka Hoshino

    IPC分类号： H01L27/12

    CPC分类号： H01L29/42384 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/4908 ,  H01L29/78612 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An object of the invention is to provide a semiconductor device having improved performance, high reliability, and a reduced chip size, in particular, to provide a semiconductor device having an MOSFET over an SOI substrate capable of maintaining its reliability while controlling the potential of a well below a gate electrode and preventing generation of parasitic capacitance. Generation of parasitic capacitance is prevented by controlling the potential of a well below a gate electrode by using a well contact plug passing through a hole portion formed in a gate electrode wiring. Generation of defects in a gate insulating film is prevented by making use of a gettering effect produced by causing an element isolation region to extend along the gate electrode.

    摘要翻译： 本发明的目的是提供一种具有改进的性能，高可靠性和减小的芯片尺寸的半导体器件，特别是提供一种在SOI衬底上具有MOSFET的半导体器件，其能够保持其可靠性，同时控制一个 远低于栅电极并防止寄生电容的产生。 通过使用穿过形成在栅电极布线中的孔部的阱接触塞来控制阱下方的阱的电位来防止寄生电容的产生。 通过利用通过使元件隔离区域沿着栅电极延伸而产生的吸杂效应来防止栅绝缘膜中的缺陷的产生。