公开(公告)号：US20070138710A1

公开(公告)日：2007-06-21

申请号：US10589092

申请日：2005-02-07

申请人： Hiroyuki Fukuyama ,  Takehiko Yoneda ,  Shigo Kikutani

发明人： Hiroyuki Fukuyama ,  Takehiko Yoneda ,  Shigo Kikutani

IPC分类号： C04B33/32 ,  B32B9/00 ,  B32B19/00

CPC分类号： H01L35/34 ,  C04B41/009 ,  C04B41/52 ,  C04B41/90 ,  C04B2111/00844 ,  H01L35/32 ,  C04B41/0072 ,  C04B41/4519 ,  C04B41/4556 ,  C04B41/5031 ,  C04B41/51 ,  C04B35/581

摘要： [PROBLEMS] To provide a metallized non-oxide ceramic shaped article having high adhesive strength between a metal layer and a substrate and the adhesion durability and to provide a process for producing the same. [MEANS FOR SOLVING PROBLEMS] The process for producing a metallized shaped article includes: a heating step of heating a non-oxide ceramic shaped article to a temperature at or above a temperature, which is 300° C. below the oxidation start temperature of the non-oxide ceramics, without substantial dissolution of oxygen in a solid solution form during heating; an oxidation step of bringing the non-oxide ceramic substrate heated in the heating step into contact with an oxidizing gas and then holding the non-oxide ceramic substrate at a temperature above the oxidation start temperature of the non-oxide ceramics to oxidize the surface of the non-oxide ceramic shaped article and thus to form an oxide layer on the surface of the non-oxide ceramic substrate; and a metallization step of forming a metal layer on the surface of the oxide layer in the non-oxide ceramic shaped article having an oxide layer on its surface produced in the oxidation step.

摘要翻译： 本发明提供一种在金属层和基材之间具有高粘合强度的金属化非氧化物陶瓷成型制品和粘合耐久性，并提供其制造方法。 用于解决问题的方法金属化成型制品的制造方法包括：将非氧化物陶瓷成型制品加热至等于或高于低于氧化物的氧化开始温度300℃的温度的加热步骤 非氧化物陶瓷，在加热期间没有固体溶液形式的氧的实质溶解; 使在加热步骤中加热的非氧化物陶瓷基板与氧化气体接触，然后将非氧化物陶瓷基板保持在高于非氧化物陶瓷的氧化开始温度的温度下氧化表面的氧化步骤 非氧化物陶瓷成形体，从而在非氧化物陶瓷基板的表面形成氧化物层; 以及金属化工序，在氧化工序中产生的表面上形成氧化物层的非氧化物陶瓷成形体的氧化物层的表面形成金属层。

公开(公告)号：US20070161494A1

公开(公告)日：2007-07-12

申请号：US10587327

申请日：2005-01-21

申请人： Hiroyuki Fukuyama ,  Takehiko Yoneda ,  Masao Ariyuki ,  Takeshi Sunaoshi ,  Hideki Sato

发明人： Hiroyuki Fukuyama ,  Takehiko Yoneda ,  Masao Ariyuki ,  Takeshi Sunaoshi ,  Hideki Sato

IPC分类号： C04B35/00 ,  B65D85/00

CPC分类号： C04B41/009 ,  C04B41/5031 ,  C04B41/87 ,  H01L21/4807 ,  H01L23/15 ,  H01L2924/0002 ,  C04B41/0072 ,  C04B41/4519 ,  C04B35/581 ,  H01L2924/00

摘要： A non-oxide ceramics having improved performances and functions by forming a high-quality oxide film on the surface of a non-oxide ceramics such as aluminum nitride. The method for the formation of the non-oxide ceramics comprises the steps of: (1) providing a non-oxide ceramics; (2) introducing the non-oxide ceramics into a furnace and then regulating the atmosphere within the furnace so as to have an oxidizing gas content of not more than 0.5 mmol in terms of total number of moles of the oxidizing gas per m3 of the inside of the furnace; (3) heating the non-oxide ceramics to a temperature at or above a temperature, which is 300° C. below the oxidation start temperature of the non-oxide ceramics, while maintaining the low-oxidizing gas atmosphere and (4) bringing the non-oxide ceramics heated in the step (3) into contact with an oxidizing gas and then holding the non-oxide ceramics at a temperature above the oxidation start temperature of the non-oxide ceramics to form an oxide layer, and that, in the step (4), until at least two min. elapses after the arrival of the temperature at or above the oxidation start temperature after the start of the contact between the non-oxide ceramics and the oxidizing gas, the pressure or partial pressure of the oxidizing gas is maintained at not more than 50 kPa.

摘要翻译： 通过在诸如氮化铝的非氧化物陶瓷的表面上形成高质量的氧化物膜而具有改进的性能和功能的非氧化物陶瓷。 形成非氧化物陶瓷的方法包括以下步骤：（1）提供非氧化物陶瓷; （2）将非氧化物陶瓷引入炉中，然后调节炉内的气氛，使得氧化气体含量以每立方米内的氧化气体的总摩尔数计不大于0.5mmol 的炉子 （3）在保持低氧化性气体气氛的同时，将非氧化物陶瓷的温度加热到低于非氧化物陶瓷的氧化开始温度300℃以下的温度，（4）使 在步骤（3）中加热的非氧化物陶瓷与氧化气体接触，然后将非氧化物陶瓷保持在高于非氧化物陶瓷的氧化开始温度的温度以形成氧化物层，并且在 步骤（4），直到至少两分钟。 在非氧化物陶瓷与氧化气体接触开始之后温度达到或高于氧化开始温度时，氧化气体的压力或分压保持在50kPa以下。

公开(公告)号：US09143110B2

公开(公告)日：2015-09-22

申请号：US14114519

申请日：2012-06-29

申请人： Kimikazu Sano ,  Hiroyuki Fukuyama ,  Makoto Nakamura ,  Hideyuki Nosaka ,  Miwa Mutoh ,  Koichi Murata

发明人： Kimikazu Sano ,  Hiroyuki Fukuyama ,  Makoto Nakamura ,  Hideyuki Nosaka ,  Miwa Mutoh ,  Koichi Murata

IPC分类号： H03G3/10 ,  H03F1/08 ,  H03G3/30

CPC分类号： H03G3/30 ,  H03G3/3084

摘要： An automatic gain control circuit (5a) includes a peak detector circuit (10) that detects the peak voltage of the output signal from a variable gain amplifier (3), an average value detection and output amplitude setting circuit (11) that detects the average voltage of the output signals from the variable gain amplifier (3) and adds a voltage ½ the desired output amplitude of the variable gain amplifier (3) to the average voltage, and a high gain amplifier (12) that amplifies the difference between the output voltage of the peak detector circuit (10) and the output voltage of the average value detection and output amplitude setting circuit (11) and controls the gain of the variable gain amplifier (3) using the amplification result as a gain control signal. The peak detector circuit (10) includes transistors (Q1, Q2, Q3), a current source (I1), and a filter circuit. The filter circuit includes a series connection of a resistor (Ra) and a capacitor (C1).

摘要翻译： 自动增益控制电路（5a）包括检测来自可变增益放大器（3）的输出信号的峰值电压的峰值检测电路（10），检测平均值的平均值检测和输出幅度设定电路（11） 来自可变增益放大器（3）的输出信号的电压，并将可变增益放大器（3）的期望输出幅度的电压½加到平均电压上;以及高增益放大器（12），放大输出 峰值检测器电路（10）的电压和平均值检测和输出幅度设置电路（11）的输出电压，并且使用放大结果来控制可变增益放大器（3）的增益作为增益控制信号。 峰值检测器电路（10）包括晶体管（Q1，Q2，Q3），电流源（I1）和滤波器电路。 滤波电路包括电阻（Ra）和电容器（C1）的串联连接。

公开(公告)号：US08397132B2

公开(公告)日：2013-03-12

申请号：US12700986

申请日：2010-02-05

申请人： Hiroyuki Fukuyama ,  Satoshi Miyazaki

发明人： Hiroyuki Fukuyama ,  Satoshi Miyazaki

IPC分类号： G11C29/00

CPC分类号： G06F11/1048

摘要： An exemplary memory device has at least one memory chip that stores data and error correcting information. An error detecting circuit in the memory chip performs a calculation on the data and error correcting information to obtain error detection information indicating the locations of bit errors in the data. The uncorrected data and the error detection information are output from the memory chip. The uncorrected data and error detection information may also be output from the memory device, or the memory device may include a memory controller chip with an error correcting circuit that uses the error detection information to correct the bit errors and outputs corrected data from the memory device.

摘要翻译： 示例性存储器件具有存储数据和纠错信息的至少一个存储器芯片。 存储器芯片中的错误检测电路对数据和纠错信息执行计算，以获得指示数据中位错误的位置的错误检测信息。 未校正的数据和错误检测信息从存储器芯片输出。 还可以从存储器件输出未校正的数据和错误检测信息，或者存储器件可以包括具有错误校正电路的存储器控​​制器芯片，其使用错误检测信息来校正位错误并从存储器件输出校正数据 。

公开(公告)号：US20120326782A1

公开(公告)日：2012-12-27

申请号：US13527512

申请日：2012-06-19

申请人： Kimikazu Sano ,  Hiroyuki Fukuyama ,  Hideyuki Nosaka ,  Makoto Nakamura ,  Koichi Murata ,  Masatoshi Tobayashi ,  Yasunobu Inabe ,  Eisuke Tsuchiya

发明人： Kimikazu Sano ,  Hiroyuki Fukuyama ,  Hideyuki Nosaka ,  Makoto Nakamura ,  Koichi Murata ,  Masatoshi Tobayashi ,  Yasunobu Inabe ,  Eisuke Tsuchiya

IPC分类号： H03G3/20

CPC分类号： H03G1/0023

摘要： In an automatic gain control circuit, a peak detection circuit detects and outputs the peak voltage of an output signal from a variable gain circuit. An average value detection/output amplitude setting circuit detects the average value voltage of an output signal from the variable gain circuit, and outputs a calculated voltage. An amplification circuit controls the gain of the variable gain circuit by amplifying the difference between the output voltages of the peak detection circuit and average value detection/output amplitude setting circuit. The number of base-emitter junctions of transistors on a path in the peak detection circuit from input ports which receive output signals from the variable gain circuit to an output port which outputs a voltage to the amplification circuit is equal to the number of base-emitter junctions of transistors on a path in the average value detection/output amplitude setting circuit.

摘要翻译： 在自动增益控制电路中，峰值检测电路检测并输出来自可变增益电路的输出信号的峰值电压。 平均值检测/输出振幅设定电路检测来自可变增益电路的输出信号的平均值电压，并输出计算出的电压。 放大电路通过放大峰值检测电路的输出电压和平均值检测/输出幅度设定电路之间的差来控制可变增益电路的增益。 从输入端口接收峰值检测电路中的路径上的晶体管的基极 - 发射极结数量，该输入端口从可变增益电路接收输出到放大电路的电压的输出端口等于基极 - 发射极 在平均值检测/输出幅度设置电路中的路径上的晶体管的结。

公开(公告)号：US20120319766A1

公开(公告)日：2012-12-20

申请号：US13527510

申请日：2012-06-19

申请人： Kimikazu Sano ,  Hiroyuki Fukuyama ,  Hideyuki Nosaka ,  Makoto Nakamura ,  Koichi Murata ,  Masatoshi Tobayashi ,  Eisuke Tsuchiya

发明人： Kimikazu Sano ,  Hiroyuki Fukuyama ,  Hideyuki Nosaka ,  Makoto Nakamura ,  Koichi Murata ,  Masatoshi Tobayashi ,  Eisuke Tsuchiya

IPC分类号： G05F3/02

CPC分类号： H03K19/017545

摘要： In a signal output circuit, an input buffer externally receives a single-phase switching instruction signal to switch a state of the output circuit a shutdown disable state or a shutdown enable state, and converts and outputs the single-phase switching instruction signal into a differential switching instruction signal. A generation control circuit outputs a generation control signal for controlling generation of a control voltage in the control voltage generation circuit based on the differential switching instruction signal. A control voltage generation circuit outputs the control voltage upon changing a value of the control voltage in accordance with a logic of the single-phase switching instruction signal. An output circuit externally receives a differential input signal, outputs a differential output signal upon impedance-converting the differential input signal, and switches between the shutdown disable state and the shutdown enable state of the differential input signal.

摘要翻译： 在信号输出电路中，输入缓冲器从外部接收单相开关指令信号，以将输出电路的状态切换到关闭禁止状态或关断使能状态，并将单相切换指令信号转换并输出到差分 切换指令信号。 一代控制电路根据差动切换指示信号输出用于控制控制电压产生电路中的控制电压产生的发电控制信号。 控制电压产生电路根据单相切换指令信号的逻辑改变控制电压的值来输出控制电压。 输出电路从外部接收差分输入信号，通过对差分输入信号进行阻抗转换来输出差分输出信号，并在差分输入信号的关断禁止状态和关断使能状态之间切换。

公开(公告)号：US20120240845A1

公开(公告)日：2012-09-27

申请号：US13512627

申请日：2010-11-29

申请人： Hiroyuki Fukuyama ,  Masanobu Azuma ,  Kazuya Takada ,  Takeshi Hattori

发明人： Hiroyuki Fukuyama ,  Masanobu Azuma ,  Kazuya Takada ,  Takeshi Hattori

IPC分类号： C30B25/14 ,  C30B25/16

CPC分类号： C30B29/403 ,  C30B23/00 ,  C30B23/007 ,  C30B25/00 ,  C30B29/62

摘要： Disclosed is a novel method wherein an aluminum nitride single crystal having good crystallinity is efficiently and easily manufactured. The method for produsing an aluminum nitride single crystal wherein nitrogen gas is circulated in the presence of a raw material gas generation source, which generates an aluminum gas or an aluminum oxide gas, and a carbon body, and then the aluminum nitride single crystal is grown under a heating condition; characterized in that, at least a part of the carbon body does not directly contact with the raw material gas generation source, at least a part of the raw material gas generation source does not directly contact with the carbon body, the raw material gas generation source and the carbon body are positioned to make a space in which a clearance between the raw material gas generation source, which does not contact with the carbon body, and the carbon body, which does not contact with the raw material gas generation source, is 0.01 to 50 mm, and a heat temperature and a nitrogen gas flow rate are set so as to satisfy a condition for aluminum nitride deposition in a space between the raw material gas generation source, which does not contact with carbon body, and the carbon body, which does not contact with raw material gas generation source.

摘要翻译： 公开了一种新颖的方法，其中具有良好结晶度的氮化铝单晶被有效且容易地制造。 在生成铝气体或氧化铝气体的原料气体发生源的存在下生成氮气的氮化铝单晶的制造方法和碳体，然后生长氮化铝单晶 在加热条件下 其特征在于，所述碳体的至少一部分不与所述原料气体发生源直接接触，所述原料气体发生源的至少一部分不与碳体直接接触，所述原料气体产生源 并且碳体被定位成使与未与碳体接触的原料气体发生源与不与原料气体发生源接触的碳体之间的间隙为0.01的空间 至50mm，并且设定加热温度和氮气流量以满足与碳体不接触的原料气体发生源与碳体之间的空间中的氮化铝沉积的条件， 其不与原料气体发生源接触。

公开(公告)号：US08137825B2

公开(公告)日：2012-03-20

申请号：US11989841

申请日：2006-08-01

申请人： Hiroyuki Fukuyama ,  Kazuya Takada ,  Akira Hakomori

发明人： Hiroyuki Fukuyama ,  Kazuya Takada ,  Akira Hakomori

IPC分类号： B32B9/00

CPC分类号： C30B29/403 ,  C30B1/10 ,  C30B25/02

摘要： In a method of manufacturing an aluminum nitride single crystal film on a substrate by heating a sapphire substrate in the presence of carbon, nitrogen and carbon monoxide, an aluminum compound which differs from the raw material sapphire substrate and the formed aluminum nitride single crystal and can control the concentration of aluminum in the heating atmosphere, such as aluminum nitride or alumina, is made existent in a reaction system to promote a reduction nitriding reaction.An aluminum nitride single crystal multi-layer substrate having an aluminum nitride single crystal film on the surface of a sapphire substrate, wherein the aluminum nitride single crystal has improved crystallinity and a low density of defects, is provided.

摘要翻译： 在通过在碳，氮和一氧化碳的存在下加热蓝宝石衬底而在衬底上制造氮化铝单晶膜的方法，与原料蓝宝石衬底和形成的氮化铝单晶不同的铝化合物 在反应体系中存在控制加热气氛中的铝的浓度如氮化铝或氧化铝以促进还原氮化反应。 提供了在蓝宝石衬底的表面上具有氮化铝单晶膜的氮化铝单晶多层衬底，其中所述氮化铝单晶具有改善的结晶度和低密度缺陷。

公开(公告)号：US07333372B2

公开(公告)日：2008-02-19

申请号：US10958658

申请日：2004-10-06

申请人： Hitoshi Tanaka ,  Hiroyuki Fukuyama ,  Takeru Yonaga

发明人： Hitoshi Tanaka ,  Hiroyuki Fukuyama ,  Takeru Yonaga

IPC分类号： G11C7/00

CPC分类号： G06F1/24

摘要： A reset circuit, which generates a reset signal for initializing an internal circuit of an integrated circuit device having an auto-loading function, includes a first register which stores a predetermined expected value data; a second register holding data which was auto-loaded; and a data comparison circuit which performs a comparison between the data held in the second register and the expected value data stored in the first register, and generates the reset signal based on a result of the comparison.

摘要翻译： 产生用于初始化具有自动加载功能的集成电路装置的内部电路的复位信号的复位电路包括存储预定期望值数据的第一寄存器; 第二个寄存器保存自动加载的数据; 以及数据比较电路，其执行保持在第二寄存器中的数据与存储在第一寄存器中的期望值数据之间的比较，并且基于比较的结果生成复位信号。

公开(公告)号：US07114113B2

公开(公告)日：2006-09-26

申请号：US10647378

申请日：2003-08-26

申请人： Takeru Yonaga ,  Hiroyuki Fukuyama ,  Hitoshi Tanaka

发明人： Takeru Yonaga ,  Hiroyuki Fukuyama ,  Hitoshi Tanaka

IPC分类号： G06F11/00

CPC分类号： G01R31/31725 ,  G01R31/31723 ,  G01R31/3187 ,  G01R31/31921 ,  G01R31/31926

摘要： A test circuit includes an input circuit for inputting data to select a test mode relative to a circuit to be tested and outputting result of selection of the test mode in synchronization with a first clock, a pattern generation circuit for responding to result of selection of the test mode, generating a test pattern in synchronization with a second clock and outputting the test pattern to the circuit to be tested and a comparator circuit for inputting result of test of the circuit to be tested in synchronization with the second clock, and comparing coincidence/non-coincidence between the result of the test and the test pattern supplied to the circuit to be tested. The test circuit further includes an output circuit for holding result of comparison by the comparator circuit and outputting the result of comparison in synchronization with the first clock.

摘要翻译： 测试电路包括输入电路，用于输入数据以选择相对于要测试的电路的测试模式，并输出与第一时钟同步的测试模式的选择结果;模式产生电路，用于响应于所选择的结果 测试模式，与第二时钟同步地产生测试模式，并将测试模式输出到要测试的电路;以及比较器电路，用于与第二时钟同步地输入要测试的电路的测试结果;以及比较符合/ 测试结果与提供给待测电路的测试模式之间不一致。 测试电路还包括输出电路，用于保持比较电路的比较结果，并与第一时钟同步地输出比较结果。