公开(公告)号：US07554178B2

公开(公告)日：2009-06-30

申请号：US11400247

申请日：2006-04-10

申请人： Hiroyuki Nakanishi ,  Kanji Natori

发明人： Hiroyuki Nakanishi ,  Kanji Natori

IPC分类号： H01L23/552

CPC分类号： H01L23/552 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor element, a first signal line connected with the semiconductor element, and a light-blocking region enclosing the semiconductor element, a first signal line pull-out region for pulling the first signal line outside the light-blocking region being provided in the light-blocking region, a first light-blocking signal line making up the first signal line being formed between the first signal line pull-out region and the semiconductor element, and the first light-blocking signal line being formed to extend along a direction which intersects a direction in which the first signal line extends toward the semiconductor element.

摘要翻译： 半导体器件包括半导体元件，与半导体元件连接的第一信号线和封装半导体元件的遮光区域，用于将遮光区域外的第一信号线拉出的第一信号线拉出区域为 设置在所述遮光区域中，构成所述第一信号线的第一遮光信号线形成在所述第一信号线引出区域和所述半导体元件之间，并且所述第一遮光信号线形成为沿着 与第一信号线朝向半导体元件延伸的方向相交的方向。

公开(公告)号：US20060244145A1

公开(公告)日：2006-11-02

申请号：US11400247

申请日：2006-04-10

申请人： Hiroyuki Nakanishi ,  Kanji Natori

发明人： Hiroyuki Nakanishi ,  Kanji Natori

IPC分类号： H01L23/52

CPC分类号： H01L23/552 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor element, a first signal line connected with the semiconductor element, and a light-blocking region enclosing the semiconductor element, a first signal line pull-out region for pulling the first signal line outside the light-blocking region being provided in the light-blocking region, a first light-blocking signal line making up the first signal line being formed between the first signal line pull-out region and the semiconductor element, and the first light-blocking signal line being formed to extend along a direction which intersects a direction in which the first signal line extends toward the semiconductor element.

公开(公告)号：US20070057894A1

公开(公告)日：2007-03-15

申请号：US11468548

申请日：2006-08-30

申请人： Kanji Natori ,  Kimihiro Maemura ,  Takashi Kumagai

发明人： Kanji Natori ,  Kimihiro Maemura ,  Takashi Kumagai

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G3/3648 ,  G09G2320/08 ,  G11C16/0433

摘要： An integrated circuit device, a first direction being a direction extending from a first side which is a shorter side of the integrated circuit device to a third side opposed to the first side, a second direction being a direction extending from a second side which is a longer side of the integrated circuit device to a fourth side opposed to the second side, includes: a first to a Nth circuit blocks (N is an integer more than 2) arranged in the first direction. One of the first to the Nth circuit blocks is a programmable ROM block in which at least a part of data programmed is stored by a user; the programmable ROM block includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines; and the plurality of word lines extend in the second direction.

摘要翻译： 集成电路器件，第一方向是从集成电路器件的短边的第一侧延伸到与第一侧相对的第三侧的方向，第二方向是从第二侧延伸的方向，第二侧为 集成电路器件的长边与第二侧相对的第四侧包括：沿第一方向布置的第一至第N电路块（N为大于2的整数）。 第一至第N电路块之一是可编程ROM块，其中编程的数据的至少一部分由用户存储; 可编程ROM块包括多个字线，多个位线和连接到多个字线和多个位线的多个存储器单元; 并且所述多个字线在所述第二方向上延伸。

公开(公告)号：US20070057314A1

公开(公告)日：2007-03-15

申请号：US11515909

申请日：2006-09-06

申请人： Kanji Natori ,  Kimihiro Maemura ,  Tomo Takaso ,  Kunio Watanabe ,  Masahiro Hayashi

发明人： Kanji Natori ,  Kimihiro Maemura ,  Tomo Takaso ,  Kunio Watanabe ,  Masahiro Hayashi

IPC分类号： H01L29/788

CPC分类号： G11C16/0416 ,  G09G3/3688 ,  G09G3/3696 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

摘要： A programmable ROM block provided in an integrated circuit device includes a memory cell having a single-layer-gate structure in which a floating gate used in common as gates of a write/read transistor and an erase transistor is opposite to a control gate formed of an impurity layer through an insulating layer. The memory cell the cell was backward has a triple-well structure including a shallow well of a first conductivity type formed on a deep well of a second conductivity type, a ring-shaped shallow well of the second conductivity type which encloses the shallow well of the first conductivity type, and top impurity regions formed in the shallow well of the first conductivity type and the ring-shaped shallow well of the second conductivity type.

摘要翻译： 设置在集成电路器件中的可编程ROM块包括具有单层栅极结构的存储单元，其中，作为写入/读取晶体管和擦除晶体管的栅极共同使用的浮动栅极与由控制栅极形成的控制栅极相反 通过绝缘层的杂质层。 电池后退的存储单元具有三阱结构，其包括形成在第二导电类型的深阱上的第一导电类型的浅阱，第二导电类型的环状浅阱，其包围浅阱 第一导电类型和形成在第一导电类型的浅阱中的顶部杂质区域和第二导电类型的环形浅阱。

公开(公告)号：US08339352B2

公开(公告)日：2012-12-25

申请号：US13300253

申请日：2011-11-18

申请人： Kanji Natori ,  Takashi Kumagai

发明人： Kanji Natori ,  Takashi Kumagai

IPC分类号： G09G3/36 ,  G06F3/038

CPC分类号： G09G3/2011 ,  G09G3/3688 ,  G09G2310/0278 ,  G09G2320/0673

摘要： An integrated circuit device includes first to Nth circuit blocks (N is an integer of two or more) disposed along the long side of the integrated circuit device. One circuit block of the first to Nth circuit blocks is a logic circuit block, and another circuit block of the first to Nth circuit blocks is a programmable ROM of which at least part of data stored therein can be programmed by a user. The logic circuit block and the programmable ROM block are adjacently disposed along a first direction. At least part of information stored in the programmable ROM block is supplied to the logic circuit block.

摘要翻译： 集成电路器件包括沿着集成电路器件的长边设置的第一至第N电路块（N为两个或更多个的整数）。 第一至第N电路块的一个电路块是逻辑电路块，第一至第N电路块的另一个电路块是其中存储的数据的至少一部分可由用户编程的可编程ROM。 逻辑电路块和可编程ROM块沿着第一方向相邻地布置。 存储在可编程ROM块中的信息的至少一部分被提供给逻辑电路块。

公开(公告)号：US06778446B2

公开(公告)日：2004-08-17

申请号：US10246665

申请日：2002-09-19

申请人： Kanji Natori

发明人： Kanji Natori

IPC分类号： G11C1604

CPC分类号： G11C16/30 ,  G11C5/145

摘要： A non-volatile semiconductor memory apparatus reduces the area occupied by circuits and thus the costs, and reduces the current consumption by providing a plurality of operating voltages by one charge pump circuit. A strong charge pump generates 5.0V and a power supply voltage of 8.0V. The power supply voltage is supplied to constant voltage circuits. The constant voltage circuits generate voltages according to the respective read, program and erase operation modes. These voltages are supplied to bit lines and control gate lines of the array block. In this manner, a plurality of operating voltages are obtained by using the power supply voltage from the charge pump to enable a read, program or erase operation for a non-volatile memory element of a twin memory cell. A plurality of operating voltages are generated by one strong charge pump, and thus the area occupied by circuits, the costs and the power consumption can be reduced.

摘要翻译： 非易失性半导体存储装置通过由一个电荷泵电路提供多个工作电压来减小电路所占用的面积，从而降低成本并降低电流消耗。 强电荷泵产生5.0V，电源电压为8.0V。 电源电压供给恒压电路。 恒压电路根据相应的读取，编程和擦除操作模式产生电压。 这些电压被提供给阵列块的位线和控制栅极线。 以这种方式，通过使用来自电荷泵的电源电压来获得多个工作电压，以对双存储单元的非易失性存储元件进行读取，编程或擦除操作。 通过一个强电荷泵产生多个工作电压，因此可以减少由电路占用的面积，成本和功耗。

公开(公告)号：US08081149B2

公开(公告)日：2011-12-20

申请号：US11515897

申请日：2006-09-06

申请人： Kanji Natori ,  Takashi Kumagai

发明人： Kanji Natori ,  Takashi Kumagai

IPC分类号： G09G3/36 ,  G06F3/038

CPC分类号： G09G3/2011 ,  G09G3/3688 ,  G09G2310/0278 ,  G09G2320/0673

摘要： An integrated circuit device includes first to Nth circuit blocks (N is an integer of two or more) disposed along the long side of the integrated circuit device. One circuit block of the first to Nth circuit blocks is a logic circuit block, and another circuit block of the first to Nth circuit blocks is a programmable ROM of which at least part of data stored therein can be programmed by a user. The logic circuit block and the programmable ROM block are adjacently disposed along a first direction. At least part of information stored in the programmable ROM block is supplied to the logic circuit block.

摘要翻译： 集成电路器件包括沿着集成电路器件的长边设置的第一至第N电路块（N为两个或更多个的整数）。 第一至第N电路块的一个电路块是逻辑电路块，第一至第N电路块的另一个电路块是其中存储的数据的至少一部分可由用户编程的可编程ROM。 逻辑电路块和可编程ROM块沿着第一方向相邻地布置。 存储在可编程ROM块中的信息的至少一部分被提供给逻辑电路块。

公开(公告)号：US06707716B2

公开(公告)日：2004-03-16

申请号：US10323921

申请日：2002-12-20

申请人： Kanji Natori

发明人： Kanji Natori

IPC分类号： G11C1604

CPC分类号： G11C29/021 ,  G11C5/145 ,  G11C8/08 ,  G11C16/12 ,  G11C16/30

摘要： In a non-volatile semiconductor memory device of the present invention, a level sense circuit controls operation of an oscillation circuit to make an output voltage of a charge pump circuit equal to a setting voltage. The level sense circuit detects a change of the output voltage of the charge pump circuit to a second setting voltage, which corresponds to a second operation mode and is set by a control circuit, after a switchover from a first operation mode to the second operation mode controlled by the control circuit. This results in detection of an end timing of operation of a discharge circuit, which is driven at the time of the switchover from the first operation mode to the second operation mode. The control circuit stops the operation of the discharge circuit, based on a result of detection of the end timing. This arrangement of the present invention effectively shortens a time period required for enabling an access at the time of the switchover of the operation mode without significantly increasing the total space of the non-volatile semiconductor memory device.

摘要翻译： 在本发明的非易失性半导体存储器件中，电平检测电路控制振荡电路的操作，使电荷泵电路的输出电压等于设定电压。 在从第一操作模式切换到第二操作模式之后，电平检测电路检测到电荷泵电路的输出电压的变化为对应于第二操作模式并由控制电路设置的第二设定电压 由控制电路控制。 这导致检测在从第一操作模式切换到第二操作模式时被驱动的放电电路的操作结束定时。 控制电路基于结束定时的检测结果停止放电电路的动作。 本发明的这种布置在不显着增加非易失性半导体存储器件的总空间的情况下，有效地缩短了在切换操作模式时能够进行访问所需的时间。

公开(公告)号：US07391668B2

公开(公告)日：2008-06-24

申请号：US11468548

申请日：2006-08-30

申请人： Kanji Natori ,  Kimihiro Maemura ,  Takashi Kumagai

发明人： Kanji Natori ,  Kimihiro Maemura ,  Takashi Kumagai

IPC分类号： G11C8/00

CPC分类号： G09G3/3611 ,  G09G3/3648 ,  G09G2320/08 ,  G11C16/0433

摘要： An integrated circuit device, a first direction being a direction extending from a first side which is a shorter side of the integrated circuit device to a third side opposed to the first side, a second direction being a direction extending from a second side which is a longer side of the integrated circuit device to a fourth side opposed to the second side, includes: a first to a Nth circuit blocks (N is an integer more than 2) arranged in the first direction. One of the first to the Nth circuit blocks is a programmable ROM block in which at least a part of data programmed is stored by a user; the programmable ROM block includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines; and the plurality of word lines extend in the second direction.

摘要翻译： 集成电路器件，第一方向是从集成电路器件的短边的第一侧延伸到与第一侧相对的第三侧的方向，第二方向是从第二侧延伸的方向，第二侧为 集成电路器件的长边与第二侧相对的第四侧包括：沿第一方向布置的第一至第N电路块（N为大于2的整数）。 第一至第N电路块之一是可编程ROM块，其中编程的数据的至少一部分由用户存储; 可编程ROM块包括多个字线，多个位线和连接到多个字线和多个位线的多个存储器单元; 并且所述多个字线在所述第二方向上延伸。

公开(公告)号：US06901009B2

公开(公告)日：2005-05-31

申请号：US10338834

申请日：2003-01-09

申请人： Kanji Natori

发明人： Kanji Natori

IPC分类号： G11C16/06 ,  G11C5/14 ,  G11C8/08 ,  G11C16/04 ,  G11C16/30 ,  H01L21/822 ,  H01L27/04 ,  H01L27/115 ,  H01L31/0328

CPC分类号： G11C8/08 ,  G11C5/145 ,  G11C16/30 ,  H01L27/115

摘要： A detection circuit detects a rising time period between a power supply ON time or a reset time and a time when a boosted voltage reaches a standby voltage, and outputs a detection signal representing a result of the detection. An oscillation circuit generates an outputs a clock signal having a constant frequency which is lower than a frequency in an ordinary state, while the detection signal is at a high level. A charge pump circuit boosts a power source voltage in response to the input clock signal of the constant frequency and causes the boosted voltage to gently rise from the power source voltage, thereby effectively interfering with an increase in reference voltage accompanied by the increase in boosted voltage.

摘要翻译： 检测电路检测电源接通时间或复位时间与升压电压达到待机电压的时间之间的上升时间，并输出表示检测结果的检测信号。 振荡电路在检测信号处于高电平时产生具有低于普通状态的频率的恒定频率的时钟信号的输出。 电荷泵电路响应于恒定频率的输入时钟信号而提高电源电压，并且使升压电压从电源电压缓缓上升，从而有效地干扰参考电压的增加，伴随着升压电压的增加 。