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公开(公告)号：US20070057314A1
公开(公告)日：2007-03-15
申请号：US11515909
申请日：2006-09-06
IPC分类号： H01L29/788
CPC分类号： G11C16/0416 , G09G3/3688 , G09G3/3696 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A programmable ROM block provided in an integrated circuit device includes a memory cell having a single-layer-gate structure in which a floating gate used in common as gates of a write/read transistor and an erase transistor is opposite to a control gate formed of an impurity layer through an insulating layer. The memory cell the cell was backward has a triple-well structure including a shallow well of a first conductivity type formed on a deep well of a second conductivity type, a ring-shaped shallow well of the second conductivity type which encloses the shallow well of the first conductivity type, and top impurity regions formed in the shallow well of the first conductivity type and the ring-shaped shallow well of the second conductivity type.
摘要翻译： 设置在集成电路器件中的可编程ROM块包括具有单层栅极结构的存储单元，其中，作为写入/读取晶体管和擦除晶体管的栅极共同使用的浮动栅极与由控制栅极形成的控制栅极相反 通过绝缘层的杂质层。 电池后退的存储单元具有三阱结构，其包括形成在第二导电类型的深阱上的第一导电类型的浅阱，第二导电类型的环状浅阱，其包围浅阱 第一导电类型和形成在第一导电类型的浅阱中的顶部杂质区域和第二导电类型的环形浅阱。
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公开(公告)号：US07391668B2
公开(公告)日：2008-06-24
申请号：US11468548
申请日：2006-08-30
申请人： Kanji Natori , Kimihiro Maemura , Takashi Kumagai
发明人： Kanji Natori , Kimihiro Maemura , Takashi Kumagai
IPC分类号： G11C8/00
CPC分类号： G09G3/3611 , G09G3/3648 , G09G2320/08 , G11C16/0433
摘要： An integrated circuit device, a first direction being a direction extending from a first side which is a shorter side of the integrated circuit device to a third side opposed to the first side, a second direction being a direction extending from a second side which is a longer side of the integrated circuit device to a fourth side opposed to the second side, includes: a first to a Nth circuit blocks (N is an integer more than 2) arranged in the first direction. One of the first to the Nth circuit blocks is a programmable ROM block in which at least a part of data programmed is stored by a user; the programmable ROM block includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines; and the plurality of word lines extend in the second direction.
摘要翻译： 集成电路器件，第一方向是从集成电路器件的短边的第一侧延伸到与第一侧相对的第三侧的方向，第二方向是从第二侧延伸的方向，第二侧为 集成电路器件的长边与第二侧相对的第四侧包括：沿第一方向布置的第一至第N电路块（N为大于2的整数）。 第一至第N电路块之一是可编程ROM块，其中编程的数据的至少一部分由用户存储; 可编程ROM块包括多个字线，多个位线和连接到多个字线和多个位线的多个存储器单元; 并且所述多个字线在所述第二方向上延伸。
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公开(公告)号：US20070057894A1
公开(公告)日：2007-03-15
申请号：US11468548
申请日：2006-08-30
申请人： Kanji Natori , Kimihiro Maemura , Takashi Kumagai
发明人： Kanji Natori , Kimihiro Maemura , Takashi Kumagai
IPC分类号： G09G3/36
CPC分类号： G09G3/3611 , G09G3/3648 , G09G2320/08 , G11C16/0433
摘要： An integrated circuit device, a first direction being a direction extending from a first side which is a shorter side of the integrated circuit device to a third side opposed to the first side, a second direction being a direction extending from a second side which is a longer side of the integrated circuit device to a fourth side opposed to the second side, includes: a first to a Nth circuit blocks (N is an integer more than 2) arranged in the first direction. One of the first to the Nth circuit blocks is a programmable ROM block in which at least a part of data programmed is stored by a user; the programmable ROM block includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines; and the plurality of word lines extend in the second direction.
摘要翻译： 集成电路器件，第一方向是从集成电路器件的短边的第一侧延伸到与第一侧相对的第三侧的方向，第二方向是从第二侧延伸的方向，第二侧为 集成电路器件的长边与第二侧相对的第四侧包括：沿第一方向布置的第一至第N电路块（N为大于2的整数）。 第一至第N电路块之一是可编程ROM块，其中编程的数据的至少一部分由用户存储; 可编程ROM块包括多个字线，多个位线和连接到多个字线和多个位线的多个存储器单元; 并且所述多个字线在所述第二方向上延伸。
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公开(公告)号：US07053442B2
公开(公告)日：2006-05-30
申请号：US10782975
申请日：2004-02-23
申请人： Kimihiro Maemura
发明人： Kimihiro Maemura
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , G11C7/18 , G11C16/0433 , H01L27/115
摘要： A nonvolatile semiconductor memory device having a small layout area includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The memory cell array includes source line diffusion layers, each of the source line diffusion layers extending along the row direction and connecting in common with the memory cells arranged in the row direction, bitline diffusion layers, element isolation regions which separate each of the bitline diffusion layers, and word gate common connection sections. Each of the memory cells includes a word gate and a select gate. One of the bitline diffusion layers is formed between two word gates adjacent in the column direction Y. Each of the word gate common connection sections is connected with the two word gates above one of the element isolation regions.
摘要翻译： 具有小布局区域的非易失性半导体存储器件包括其中多个存储单元在行方向和列方向上排列的存储单元阵列。 存储单元阵列包括源极线扩散层，每个源极线扩散层沿着行方向延伸并且与沿行方向布置的存储单元共同连接，位线扩散层，将每个位线扩散分离的元件隔离区域 层和字门公共连接部分。 每个存储器单元包括字门和选择门。 位线扩散层之一形成在与列方向Y相邻的两个字门之间。每个字门公共连接部分与元件隔离区域之一上的两个字门连接。
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公开(公告)号：US07285817B2
公开(公告)日：2007-10-23
申请号：US11223679
申请日：2005-09-09
IPC分类号： H01L29/788
CPC分类号： H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor layer having a shading target region; a semiconductor element provided on the semiconductor layer in the shading target region; a first interlayer dielectric provided on the semiconductor element; a plurality of first shading layers provided on the first interlayer dielectric; a second interlayer dielectric provided on at least the first shading layers; and a second shading layer provided on the second interlayer dielectric and having a predetermined pattern. The second shading layer has such a pattern that the second shading layer is positioned at least between the adjacent first shading layers.
摘要翻译： 半导体器件包括：具有阴影目标区域的半导体层; 设置在阴影对象区域的半导体层上的半导体元件; 设置在所述半导体元件上的第一层间电介质; 设置在所述第一层间电介质上的多个第一遮光层; 至少设置在第一遮光层上的第二层间电介质; 以及设置在第二层间电介质上并具有预定图案的第二遮光层。 第二遮光层具有使第二遮光层至少位于相邻的第一遮光层之间的图案。
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公开(公告)号：US20080012141A1
公开(公告)日：2008-01-17
申请号：US11901477
申请日：2007-09-17
IPC分类号： H01L23/52
CPC分类号： H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor layer having a shading target region; a semiconductor element provided on the semiconductor layer in the shading target region; a first interlayer dielectric provided on the semiconductor element; a plurality of first shading layers provided on the first interlayer dielectric; a second interlayer dielectric provided on at least the first shading layers; and a second shading layer provided on the second interlayer dielectric and having a predetermined pattern. The second shading layer has such a pattern that the second shading layer is positioned at least between the adjacent first shading layers.
摘要翻译： 半导体器件包括：具有阴影目标区域的半导体层; 设置在阴影对象区域的半导体层上的半导体元件; 设置在所述半导体元件上的第一层间电介质; 设置在所述第一层间电介质上的多个第一遮光层; 至少设置在第一遮光层上的第二层间电介质; 以及设置在第二层间电介质上并具有预定图案的第二遮光层。 第二遮光层具有使第二遮光层至少位于相邻的第一遮光层之间的图案。
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公开(公告)号：US20060055044A1
公开(公告)日：2006-03-16
申请号：US11223679
申请日：2005-09-09
IPC分类号： H01L23/52
CPC分类号： H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor layer having a shading target region; a semiconductor element provided on the semiconductor layer in the shading target region; a first interlayer dielectric provided on the semiconductor element; a plurality of first shading layers provided on the first interlayer dielectric; a second interlayer dielectric provided on at least the first shading layers; and a second shading layer provided on the second interlayer dielectric and having a predetermined pattern. The second shading layer has such a pattern that the second shading layer is positioned at least between the adjacent first shading layers.
摘要翻译： 半导体器件包括：具有阴影目标区域的半导体层; 设置在阴影对象区域的半导体层上的半导体元件; 设置在所述半导体元件上的第一层间电介质; 设置在所述第一层间电介质上的多个第一遮光层; 至少设置在第一遮光层上的第二层间电介质; 以及设置在第二层间电介质上并具有预定图案的第二遮光层。 第二遮光层具有使第二遮光层至少位于相邻的第一遮光层之间的图案。
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8.发明申请Nonvolatile memory device and data write method for nonvolatile memory device 有权非易失性存储器件和非易失性存储器件的数据写入方法公开(公告)号：US20060023509A1
公开(公告)日：2006-02-02
申请号：US11176324
申请日：2005-07-08
IPC分类号： G11C16/04
CPC分类号： G11C16/0433
摘要： A nonvolatile memory device, wherein each of memory cells includes one of nonvolatile memory elements and one of wordline switches, wherein each of the wordlines connects in common gate electrodes of the wordline switches of memory cells arranged in the row direction; wherein each of the bitlines connects in common the wordline switches of memory cells arranged in the column direction; and wherein one of the first control gate lines connects in common control gate electrodes of the nonvolatile memory elements of M memory cells in one of memory cell blocks (M is an integer equal to or greater than 2); and wherein, when writing data into a desired memory cell, the wordline switches of the memory cells are turned ON by applying a wordline write voltage to a wordlines corresponding to the desired memory cell, a bitline write voltage is applied to the bitlines connected to the memory cells, and a control gate line write voltage is applied to one of the first control gate lines disposed in the memory cell block.
摘要翻译： 一种非易失性存储器件，其中每个存储器单元包括非易失性存储器元件和字线开关中的一个，其中每个字线连接在沿行方向布置的存储器单元的字线开关的公共栅电极中; 其中每个位线共同地连接在列方向上布置的存储器单元的字线开关; 并且其中一个第一控制栅极线连接在存储单元块之一中的M个存储单元的非易失性存储元件的公共控制栅极中（M为等于或大于2的整数）; 并且其中当将数据写入期望的存储单元时，通过将字线写入电压施加到对应于期望的存储单元的字线来使存储单元的字线切换为ON，位线写入电压被施加到连接到所述存储单元的位线 存储单元和控制栅线写入电压被施加到设置在存储单元块中的第一控制栅极线之一。
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公开(公告)号：US20050275009A1
公开(公告)日：2005-12-15
申请号：US11148302
申请日：2005-06-09
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28273 , G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/7883
摘要： A nonvolatile memory device includes: a semiconductor layer of a first conductivity type in which a first region, a second region, and a third region are partitioned by an isolation insulating layer; a semiconductor section of a second conductivity type provided in the first region and functioning as a control gate; a semiconductor section of the first conductivity type provided in the second region; a semiconductor section of the second conductivity type provided in the third region; an insulating layer provided on the semiconductor layer in the first to third regions; a floating gate electrode provided on the insulating layer across the first to third regions; impurity regions of the first conductivity type provided on each side of the floating gate electrode in the first region; impurity regions of the second conductivity type provided on each side of the floating gate electrode in the second region and functioning as either a source region or a drain region; and impurity regions of the first conductivity type provided on each side of the floating gate electrode in the third region and functioning as either a source region or a drain region.
摘要翻译： 非易失性存储器件包括：第一导电类型的半导体层，其中第一区域，第二区域和第三区域被隔离绝缘层分隔; 第二导电类型的半导体部分，设置在第一区域中并用作控制栅极; 设置在第二区域中的第一导电类型的半导体部分; 设置在第三区域中的第二导电类型的半导体部分; 设置在第一至第三区域的半导体层上的绝缘层; 在第一至第三区域上设置在绝缘层上的浮栅电极; 设置在第一区域中的浮置栅电极的每一侧上的第一导电类型的杂质区域; 第二导电类型的杂质区域设置在第二区域中的浮置栅电极的每一侧上并且用作源极区域或漏极区域; 以及设置在第三区域中的浮栅的每一侧上的第一导电类型的杂质区，并且用作源区或漏区。
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公开(公告)号：US07531864B2
公开(公告)日：2009-05-12
申请号：US11148302
申请日：2005-06-09
IPC分类号： H01L29/76
CPC分类号： H01L21/28273 , G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/7883
摘要： A nonvolatile memory device includes: a semiconductor layer of a first conductivity type in which a first region, a second region, and a third region are partitioned by an isolation insulating layer; a semiconductor section of a second conductivity type provided in the first region and functioning as a control gate; a semiconductor section of the first conductivity type provided in the second region; a semiconductor section of the second conductivity type provided in the third region; an insulating layer provided on the semiconductor layer in the first to third regions; a floating gate electrode provided on the insulating layer across the first to third regions; impurity regions of the first conductivity type provided on each side of the floating gate electrode in the first region; impurity regions of the second conductivity type provided on each side of the floating gate electrode in the second region and functioning as either a source region or a drain region; and impurity regions of the first conductivity type provided on each side of the floating gate electrode in the third region and functioning as either a source region or a drain region.
摘要翻译： 非易失性存储器件包括：第一导电类型的半导体层，其中第一区域，第二区域和第三区域被隔离绝缘层分隔; 第二导电类型的半导体部分，设置在第一区域中并用作控制栅极; 设置在第二区域中的第一导电类型的半导体部分; 设置在第三区域中的第二导电类型的半导体部分; 设置在第一至第三区域的半导体层上的绝缘层; 在第一至第三区域上设置在绝缘层上的浮栅电极; 设置在第一区域中的浮置栅电极的每一侧上的第一导电类型的杂质区域; 第二导电类型的杂质区域设置在第二区域中的浮置栅电极的每一侧上并且用作源极区域或漏极区域; 以及设置在第三区域中的浮栅的每一侧上的第一导电类型的杂质区，并且用作源区或漏区。
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