-
公开(公告)号：US07391668B2
公开(公告)日：2008-06-24
申请号：US11468548
申请日：2006-08-30
申请人： Kanji Natori , Kimihiro Maemura , Takashi Kumagai
发明人： Kanji Natori , Kimihiro Maemura , Takashi Kumagai
IPC分类号： G11C8/00
CPC分类号： G09G3/3611 , G09G3/3648 , G09G2320/08 , G11C16/0433
摘要： An integrated circuit device, a first direction being a direction extending from a first side which is a shorter side of the integrated circuit device to a third side opposed to the first side, a second direction being a direction extending from a second side which is a longer side of the integrated circuit device to a fourth side opposed to the second side, includes: a first to a Nth circuit blocks (N is an integer more than 2) arranged in the first direction. One of the first to the Nth circuit blocks is a programmable ROM block in which at least a part of data programmed is stored by a user; the programmable ROM block includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines; and the plurality of word lines extend in the second direction.
摘要翻译： 集成电路器件，第一方向是从集成电路器件的短边的第一侧延伸到与第一侧相对的第三侧的方向，第二方向是从第二侧延伸的方向，第二侧为 集成电路器件的长边与第二侧相对的第四侧包括：沿第一方向布置的第一至第N电路块（N为大于2的整数）。 第一至第N电路块之一是可编程ROM块，其中编程的数据的至少一部分由用户存储; 可编程ROM块包括多个字线，多个位线和连接到多个字线和多个位线的多个存储器单元; 并且所述多个字线在所述第二方向上延伸。
-
公开(公告)号：US20070057894A1
公开(公告)日：2007-03-15
申请号：US11468548
申请日：2006-08-30
申请人： Kanji Natori , Kimihiro Maemura , Takashi Kumagai
发明人： Kanji Natori , Kimihiro Maemura , Takashi Kumagai
IPC分类号： G09G3/36
CPC分类号： G09G3/3611 , G09G3/3648 , G09G2320/08 , G11C16/0433
摘要： An integrated circuit device, a first direction being a direction extending from a first side which is a shorter side of the integrated circuit device to a third side opposed to the first side, a second direction being a direction extending from a second side which is a longer side of the integrated circuit device to a fourth side opposed to the second side, includes: a first to a Nth circuit blocks (N is an integer more than 2) arranged in the first direction. One of the first to the Nth circuit blocks is a programmable ROM block in which at least a part of data programmed is stored by a user; the programmable ROM block includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines; and the plurality of word lines extend in the second direction.
摘要翻译： 集成电路器件，第一方向是从集成电路器件的短边的第一侧延伸到与第一侧相对的第三侧的方向，第二方向是从第二侧延伸的方向，第二侧为 集成电路器件的长边与第二侧相对的第四侧包括：沿第一方向布置的第一至第N电路块（N为大于2的整数）。 第一至第N电路块之一是可编程ROM块，其中编程的数据的至少一部分由用户存储; 可编程ROM块包括多个字线，多个位线和连接到多个字线和多个位线的多个存储器单元; 并且所述多个字线在所述第二方向上延伸。
-
公开(公告)号：US08339352B2
公开(公告)日：2012-12-25
申请号：US13300253
申请日：2011-11-18
申请人： Kanji Natori , Takashi Kumagai
发明人： Kanji Natori , Takashi Kumagai
CPC分类号： G09G3/2011 , G09G3/3688 , G09G2310/0278 , G09G2320/0673
摘要： An integrated circuit device includes first to Nth circuit blocks (N is an integer of two or more) disposed along the long side of the integrated circuit device. One circuit block of the first to Nth circuit blocks is a logic circuit block, and another circuit block of the first to Nth circuit blocks is a programmable ROM of which at least part of data stored therein can be programmed by a user. The logic circuit block and the programmable ROM block are adjacently disposed along a first direction. At least part of information stored in the programmable ROM block is supplied to the logic circuit block.
摘要翻译： 集成电路器件包括沿着集成电路器件的长边设置的第一至第N电路块（N为两个或更多个的整数）。 第一至第N电路块的一个电路块是逻辑电路块，第一至第N电路块的另一个电路块是其中存储的数据的至少一部分可由用户编程的可编程ROM。 逻辑电路块和可编程ROM块沿着第一方向相邻地布置。 存储在可编程ROM块中的信息的至少一部分被提供给逻辑电路块。
-
公开(公告)号：US08081149B2
公开(公告)日：2011-12-20
申请号：US11515897
申请日：2006-09-06
申请人： Kanji Natori , Takashi Kumagai
发明人： Kanji Natori , Takashi Kumagai
CPC分类号： G09G3/2011 , G09G3/3688 , G09G2310/0278 , G09G2320/0673
摘要： An integrated circuit device includes first to Nth circuit blocks (N is an integer of two or more) disposed along the long side of the integrated circuit device. One circuit block of the first to Nth circuit blocks is a logic circuit block, and another circuit block of the first to Nth circuit blocks is a programmable ROM of which at least part of data stored therein can be programmed by a user. The logic circuit block and the programmable ROM block are adjacently disposed along a first direction. At least part of information stored in the programmable ROM block is supplied to the logic circuit block.
摘要翻译： 集成电路器件包括沿着集成电路器件的长边设置的第一至第N电路块（N为两个或更多个的整数）。 第一至第N电路块的一个电路块是逻辑电路块，第一至第N电路块的另一个电路块是其中存储的数据的至少一部分可由用户编程的可编程ROM。 逻辑电路块和可编程ROM块沿着第一方向相邻地布置。 存储在可编程ROM块中的信息的至少一部分被提供给逻辑电路块。
-
公开(公告)号：US20070057896A1
公开(公告)日：2007-03-15
申请号：US11515897
申请日：2006-09-06
申请人： Kanji Natori , Takashi Kumagai
发明人： Kanji Natori , Takashi Kumagai
IPC分类号： G09G3/36
CPC分类号： G09G3/2011 , G09G3/3688 , G09G2310/0278 , G09G2320/0673
摘要： An integrated circuit device includes first to Nth circuit blocks (N is an integer of two or more) disposed along the long side of the integrated circuit device. One circuit block of the first to Nth circuit blocks is a logic circuit block, and another circuit block of the first to Nth circuit blocks is a programmable ROM of which at least part of data stored therein can be programmed by a user. The logic circuit block and the programmable ROM block are adjacently disposed along a first direction. At least part of information stored in the programmable ROM block is supplied to the logic circuit block.
摘要翻译： 集成电路器件包括沿着集成电路器件的长边设置的第一至第N电路块（N为两个或更多个的整数）。 第一至第N电路块的一个电路块是逻辑电路块，第一至第N电路块的另一个电路块是其中存储的数据的至少一部分可由用户编程的可编程ROM。 逻辑电路块和可编程ROM块沿着第一方向相邻地布置。 存储在可编程ROM块中的信息的至少一部分被提供给逻辑电路块。
-
6.发明授权公开(公告)号：US08896316B2
公开(公告)日：2014-11-25
申请号：US13582661
申请日：2010-06-17
CPC分类号： C01B13/11 , G01R19/2513 , G01R31/025 , G01R31/3277 , G01R35/00
摘要： In a device having capacitive loads in which a plurality of capacitive loads are connected in parallel, power is supplied from an AC power source to a load group comprising the plurality of capacitive loads, the load group is divided into a plurality of small load groups, and a current detecting sensor for detecting a current which flows in at least one small load group at a side which is closer to the load side than a branch point at which the load group is divided into the plurality of small load groups and a current abnormality detecting part for determining an abnormality of a load by a current detecting signal which is detected by the current detecting sensor are equipped.
摘要翻译： 在具有并联连接多个容性负载的容性负载的装置中，从AC电源向包括多个容性负载的负载组提供电力，负载组被分成多个小负载组， 以及电流检测传感器，用于检测在负载组被分割成多个小负载组的分支点处，在比靠近负载侧的一侧的至少一个小负载组中流动的电流和电流异常 检测由电流检测传感器检测出的电流检测信号确定负载异常的检测部件。
-
7.发明申请公开(公告)号：US20120319696A1
公开(公告)日：2012-12-20
申请号：US13582661
申请日：2010-06-17
CPC分类号： C01B13/11 , G01R19/2513 , G01R31/025 , G01R31/3277 , G01R35/00
摘要： In a device having capacitive loads in which a plurality of capacitive loads are connected in parallel, power is supplied from an AC power source to a load group comprising the plurality of capacitive loads, the load group is divided into a plurality of small load groups, and a current detecting sensor for detecting a current which flows in at least one small load group at a side which is closer to the load side than a branch point at which the load group is divided into the plurality of small load groups and a current abnormality detecting part for determining an abnormality of a load by a current detecting signal which is detected by the current detecting sensor are equipped.
摘要翻译： 在具有并联连接多个容性负载的容性负载的装置中，从AC电源向包括多个容性负载的负载组提供电力，负载组被分成多个小负载组， 以及电流检测传感器，用于检测在负载组被分割成多个小负载组的分支点处，在比靠近负载侧的一侧的至少一个小负载组中流动的电流和电流异常 检测由电流检测传感器检测出的电流检测信号确定负载异常的检测部件。
-
8.发明授权Data processing system having data reproduction independent of data processing 有权具有独立于数据处理的数据再现的数据处理系统公开(公告)号：US08159766B2
公开(公告)日：2012-04-17
申请号：US11434723
申请日：2006-05-17
申请人： Toshiyuki Arai , Takashi Kumagai , Hajime Inai , Hiroaki Sato , Fumitake Yodo , Masami Oyama
发明人： Toshiyuki Arai , Takashi Kumagai , Hajime Inai , Hiroaki Sato , Fumitake Yodo , Masami Oyama
IPC分类号： G11B5/00
CPC分类号： G11B31/00 , G11B20/00007 , G11B20/10527 , G11B27/005 , G11B27/034 , G11B27/105 , G11B27/11 , G11B27/329 , G11B27/34 , G11B2220/213 , G11B2220/2525 , G11B2220/2545 , G11B2220/2562 , H04R5/02
摘要： An information-processing apparatus includes a processing unit that compresses inputted data to produce compressed data of a first compressed format. The information-processing apparatus also includes a storage unit that stores the compressed data in a storage medium. The processing unit decompresses data, stored in the storage medium, of a second compressed format to produce decompressed data. Further, the processing unit controls the storage unit to store the compressed data of the first compressed format in the storage medium while the processing unit simultaneously decompresses the data, stored in the storage medium, of the second compressed format and reproduces the decompressed data. The first compressed format is different than the second compressed format.
摘要翻译： 信息处理装置包括：处理单元，其压缩输入的数据以产生第一压缩格式的压缩数据。 信息处理装置还包括将压缩数据存储在存储介质中的存储单元。 处理单元将存储在存储介质中的数据解压缩第二压缩格式以产生解压缩数据。 此外，处理单元控制存储单元将存储介质中的第一压缩格式的压缩数据存储在存储介质中，同时处理单元将存储在存储介质中的数据解压缩第二压缩格式，并再现解压缩数据。 第一种压缩格式与第二种压缩格式不同。
-
公开(公告)号：US20120019566A1
公开(公告)日：2012-01-26
申请号：US13137995
申请日：2011-09-23
申请人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号： G09G5/10
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译： 集成电路装置包括第一至第N电路块CB1至CBN，沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域， 在第一至第N电路块CB1至CBN的D4侧。 使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间，作为信号线和电源线中的至少一个。 使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上，作为信号线和电源线中的至少一个。
-
公开(公告)号：US08054710B2
公开(公告)日：2011-11-08
申请号：US11477670
申请日：2006-06-30
申请人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号： G11C8/00
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译： 集成电路装置包括第一至第N电路块CB1至CBN，沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域， 在第一至第N电路块CB1至CBN的D4侧。 使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间，作为信号线和电源线中的至少一个。 使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上，作为信号线和电源线中的至少一个。
-
-
-
-
-
-
-
-
-
搜索结果
145 条记录 (耗时 0.023 秒)
