公开(公告)号：US20120307863A1

公开(公告)日：2012-12-06

申请号：US13421047

申请日：2012-03-15

申请人： Hiroyuki TADA ,  Masato ASAHARA ,  Yoshihiro UEDA ,  Hideki AOKI ,  Akira MINOURA

发明人： Hiroyuki TADA ,  Masato ASAHARA ,  Yoshihiro UEDA ,  Hideki AOKI ,  Akira MINOURA

IPC分类号： G01K13/00

CPC分类号： G01K13/02 ,  G01K2013/024 ,  G01K2205/04

摘要： An exhaust gas temperature detection sensor is arranged at a predetermined position outside a muffler, or at a predetermined position outside an exhaust pipe constituting an exhaust gas flow passage on a more downstream side than the muffler in an exhaust direction. The sensor detects that an atmosphere temperature at the predetermined position outside the muffler has reached a predetermined temperature based on an increase in a temperature inside the muffler, or detects that an atmosphere temperature at the predetermined position outside the exhaust pipe has reached a predetermined temperature based on an increase in a temperature of an exhaust gas inside the exhaust pipe.

摘要翻译： 排气温度检测传感器布置在消声器外部的预定位置处，或者在构成排气流路的排气管外侧的预定位置处布置在排气方向上比消声器更下游侧的排气管温度检测传感器。 该传感器检测到消声器外的预定位置处的气氛温度已基于消音器内部的温度升高而达到预定温度，或者检测到排气管外部的预定位置处的气氛温度已达到预定温度 在排气管内的排气温度上升。

公开(公告)号：US20110259012A1

公开(公告)日：2011-10-27

申请号：US13046229

申请日：2011-03-11

申请人： Hiroyuki TADA ,  Masato ASAHARA ,  Yoshihiro UEDA ,  Eiji SATO ,  Akira MINOURA

发明人： Hiroyuki TADA ,  Masato ASAHARA ,  Yoshihiro UEDA ,  Eiji SATO ,  Akira MINOURA

IPC分类号： F01N3/00

CPC分类号： F01N3/055 ,  F01P5/06 ,  F01P2001/005 ,  F01P2060/16 ,  Y02T10/20

摘要： A working vehicle has a cooling fan provided on a first side of an engine to blow air to the engine; a muffler main body provided on a second side thereof in a position lower than an upper surface of a head cover of the engine; and an exhaust pipe exposed in a position facing an air blowing path of the cooling fan higher than the upper surface of the head cover of the engine to discharge exhaust from the muffler main body.

摘要翻译： 工作车辆具有设置在发动机的第一侧上以将空气吹送到发动机的冷却风扇; 消声器主体，其设置在比所述发动机的头罩的上表面低的位置的第二侧上; 以及排气管，其在与所述发动机的头罩的上表面相比高于所述冷却风扇的空气吹送路径的位置处露出，以从所述消声器主体排出排气。

公开(公告)号：US20120023886A1

公开(公告)日：2012-02-02

申请号：US13046278

申请日：2011-03-11

申请人： Akira MINOURA ,  Yoshihiro UEDA ,  Kuninosuke IWATA ,  Hiroyuki TADA ,  Yoshiyuki ESAKI

发明人： Akira MINOURA ,  Yoshihiro UEDA ,  Kuninosuke IWATA ,  Hiroyuki TADA ,  Yoshiyuki ESAKI

IPC分类号： A01D34/73

CPC分类号： A01D34/82

摘要： A riding mower having left and right driving rear wheels independently drivable forward and backward and a pair of left and right steerable front wheels is provided with a support device capable of being mounted with a cylindrical gas cylinder in a horizontal position on an external side of a rollover projection frame. The support device is provided such that the mounted gas cylinder is positioned along front and rear of the rollover protection frame and is mounted in a tilted state in which the central axis of the cylindrical gas cylinder is closer to a central side in a lateral direction of a vehicle body toward a rear side from a plan view.

摘要翻译： 一种具有左右驾驶后轮的骑马割草机，其前后独立地驱动，并且一对左右可转向前轮设置有能够在圆筒状气瓶的外侧安装有圆筒形气瓶的支撑装置 翻转投影框架。 支撑装置被设置成使得安装的气瓶沿着翻转保护框架的前后定位并且以倾斜状态安装，其中圆柱形气瓶的中心轴线更靠近中心侧 从平面图朝向后方的车体。

公开(公告)号：US20090201710A1

公开(公告)日：2009-08-13

申请号：US12367792

申请日：2009-02-09

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C5/02 ,  G11C7/06

CPC分类号： G11C7/14 ,  G11C7/062 ,  G11C11/5614 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0054 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72

摘要： A semiconductor memory device comprises a plurality of cell arrays, each cell array including a plurality of mutually parallel word lines, a plurality of mutually parallel bit lines disposed to cross these word lines, and a plurality of cells connected to the intersections of these word lines and bit lines, respectively, one portion of the cell arrays forming a memory cell array that has the cells as memory cells, and another portion of the cell arrays forming a reference cell array that has the cells as reference cells. A cell selection circuit is operative to select from the memory cell array a memory cell whose data is to be read, and to select from the reference cell array a reference cell at a position corresponding to a position of the memory cell selected in the memory cell array. A sense amplifier circuit is operative to detect and compare a current or a voltage of the selected memory cell with a current or a voltage of the selected reference cell, and thereby read data of the memory cell.

摘要翻译： 一种半导体存储器件包括多个单元阵列，每个单元阵列包括多个相互平行的字线，多个相互平行的位线布置成与这些字线交叉，以及多个单元，连接到这些字线的交点 和位线，分别形成具有作为存储单元的单元的存储单元阵列的单元阵列的一部分，以及形成具有单元作为参考单元的参考单元阵列的单元阵列的另一部分。 小区选择电路可操作以从存储单元阵列中选择要读取其数据的存储单元，并从参考单元阵列中选择与在存储单元中选择的存储单元的位置对应的位置处的参考单元 数组。 读出放大器电路用于检测并比较所选存储单元的电流或电压与所选参考单元的电流或电压，从而读取存储单元的数据。

公开(公告)号：US20090190391A1

公开(公告)日：2009-07-30

申请号：US12356722

申请日：2009-01-21

申请人： Kiyotaro ITAGAKI ,  Yoshihiro UEDA

发明人： Kiyotaro ITAGAKI ,  Yoshihiro UEDA

IPC分类号： G11C11/02 ,  G11C11/416 ,  G11C8/08

CPC分类号： G11C11/1675 ,  G11C11/1673

摘要： A word line voltage is applied to a plurality of word lines. A read/write voltage is applied to a plurality of bit lines. The read/write voltage is applied to a plurality of source lines. A word line selector selects the word line and applies the word line voltage. A driver applies a predetermined voltage to the bit line and the source line, thereby supplying a current to the memory cell. A read circuit reads a first current having flowed through the memory cell, and determines data stored in the memory cell. When performing the read, the driver supplies a second current to second bit lines among other bit lines, which are adjacent to the first bit line through which the first current has flowed. The second current generates a magnetic field in a direction to suppress a write error in the memory cell from which data is to be read.

摘要翻译： 字线电压被施加到多个字线。 读/写电压施加到多个位线。 读/写电压被施加到多条源极线。 字线选择器选择字线并施加字线电压。 驱动器将预定电压施加到位线和源极线，从而向存储器单元提供电流。 读取电路读取已经流过存储器单元的第一电流，并且确定存储在存储单元中的数据。 当执行读取时，驱动器向与第一电流流过的第一位线相邻的其它位线中的第二位线提供第二电流。 第二电流在抑制要从其读取数据的存储单元中的写入错误的方向上产生磁场。

公开(公告)号：US20120320665A1

公开(公告)日：2012-12-20

申请号：US13422110

申请日：2012-03-16

申请人： Yoshihiro UEDA ,  Kosuke HATSUDA

发明人： Yoshihiro UEDA ,  Kosuke HATSUDA

IPC分类号： G11C11/00

CPC分类号： G11C11/1673

摘要： A semiconductor memory includes a first memory cell including: a first resistance change element and a first select transistor. The semiconductor memory includes a second memory cell including: a second select transistor and a second resistance change element. The semiconductor memory includes a third memory cell including: a third select transistor and a third resistance change element, the third memory cell acting as a reference cell. The semiconductor memory includes a fourth memory cell including: a fourth resistance change element and a fourth select transistor, the fourth memory cell acting as a reference cell.

摘要翻译： 半导体存储器包括：第一存储单元，包括：第一电阻变化元件和第一选择晶体管。 半导体存储器包括第二存储单元，其包括：第二选择晶体管和第二电阻变化元件。 半导体存储器包括第三存储单元，第三存储单元包括：第三选择晶体管和第三电阻变化元件，第三存储单元用作参考单元。 半导体存储器包括：第四存储单元，包括：第四电阻变化元件和第四选择晶体管，第四存储单元用作参考单元。

公开(公告)号：US20100208512A1

公开(公告)日：2010-08-19

申请号：US12709256

申请日：2010-02-19

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C11/00

CPC分类号： G11C17/12 ,  G11C13/0002 ,  G11C14/0081 ,  G11C14/009

摘要： A latch circuit is connected to a first common node, a first, second output node, and a first, second connection node. A first resistance change element is connected to the first connection node, and a second common node. A second resistance change element is connected to the second connection node, and the second common node. When a first data is stored, voltages of the first common node, second common node, and first output node are set at a first reference voltage, and a voltage of the second output node is set at a second reference voltage. When a second data is stored, voltages of the first common node, second common node, and second output node are set at the first reference voltage, and a voltage of the first output node is set at the second reference voltage.

摘要翻译： 锁存电路连接到第一公共节点，第一，第二输出节点和第一，第二连接节点。 第一电阻变化元件连接到第一连接节点和第二公共节点。 第二电阻变化元件连接到第二连接节点和第二公共节点。 当存储第一数据时，将第一公共节点，第二公共节点和第一输出节点的电压设置为第一参考电压，并将第二输出节点的电压设置为第二参考电压。 当存储第二数据时，将第一公共节点，第二公共节点和第二输出节点的电压设置为第一参考电压，并且将第一输出节点的电压设置为第二参考电压。

公开(公告)号：US20090010045A1

公开(公告)日：2009-01-08

申请号：US12164410

申请日：2008-06-30

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C11/02

CPC分类号： G11C11/15 ,  G11C11/1673

摘要： A MRAM includes a first magnetoresistive effect (MR) element that takes a low and high resistance states. A second MR element is fixed to a low or high resistance state. First and second MOSFETs are connected to the first and second MR elements, respectively. A sense amplifier amplifies a difference between values of current flowing through the first and second MOSFETs. A current circuit outputs reference current whose value lies between current flowing through the first MR element of the low and high resistance states. A third MOSFET has one end that receives the reference current and is connected to its own gate terminal. The gate terminal of the second MOSFET receives the same potential as the gate terminal of the third MOSFET. A first resistance element is connected to the others end of the third MOSFET and has the same resistance as the second magnetoresistive effect element.

摘要翻译： MRAM包括采用低和高电阻状态的第一磁阻效应（MR）元件。 第二MR元件固定为低电阻或高电阻状态。 第一和第二MOSFET分别连接到第一和第二MR元件。 读出放大器放大流经第一和第二MOSFET的电流值之差。 电流电路输出其值位于流过低电阻状态和高电阻状态的第一MR元件的电流之间的参考电流。 第三个MOSFET的一端接收参考电流并连接到其自己的栅极端子。 第二MOSFET的栅极端子接收与第三MOSFET的栅极端子相同的电位。 第一电阻元件连接到第三MOSFET的另一端，并且具有与第二磁阻效应元件相同的电阻。

公开(公告)号：US20080043514A1

公开(公告)日：2008-02-21

申请号：US11781443

申请日：2007-07-23

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C11/00

CPC分类号： G11C7/02 ,  G11C7/18 ,  G11C11/1675 ,  G11C13/0004

摘要： A semiconductor memory according to examples of the present invention includes a word line extending in a first direction, first, second and third bit lines extending in a second direction, a first cell unit connected between the first and second bit lines, a second cell unit connected between the first and third bit lines, and a controller CNT which executes write to a first resistance change element under the condition that the word line is made active and potentials of the first and third bit lines are equalized, and which executes write to a second resistance change element under the condition that the word line is made active and potentials of the first and second bit lines are equalized.

摘要翻译： 根据本发明的示例的半导体存储器包括在第一方向上延伸的字线，在第二方向上延伸的第一，第二和第三位线，连接在第一和第二位线之间的第一单元单元，第二单元单元 连接在第一和第三位线之间的控制器CNT，以及在使字线有效并且第一和第三位线的电位相等的条件下执行写入第一电阻变化元件的控制器CNT，并且执行写入到 第二电阻变化元件在使字线有效并且第一和第二位线的电位相等的条件下。

公开(公告)号：US20120069629A1

公开(公告)日：2012-03-22

申请号：US13234587

申请日：2011-09-16

申请人： Yoshihiro UEDA ,  Akira KATAYAMA ,  Ryousuke TAKIZAWA

发明人： Yoshihiro UEDA ,  Akira KATAYAMA ,  Ryousuke TAKIZAWA

IPC分类号： G11C11/00 ,  G11C7/06 ,  G11C17/16

CPC分类号： G11C13/0023 ,  G11C7/065 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C17/143 ,  G11C2013/0054

摘要： According to one embodiment, a semiconductor memory device includes a first reference cell being arranged in a first cell array, and a plurality of first fuse cells being arranged in the first cell array. The first reference cell and the plurality of first fuse cells are arranged on the same row or column.

摘要翻译： 根据一个实施例，半导体存储器件包括布置在第一单元阵列中的第一参考单元，以及布置在第一单元阵列中的多个第一熔丝单元。 第一参考单元和多个第一保险丝单元布置在同一行或列上。