公开(公告)号：US08520465B2

公开(公告)日：2013-08-27

申请号：US13235426

申请日：2011-09-18

申请人： Kosuke Hatsuda

发明人： Kosuke Hatsuda

IPC分类号： G11C8/00

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/30

摘要： According to one embodiment, a semiconductor storage device includes a transistor, a first node, a first capacitor, a first switch, and a second switch. One end of the transistor is connected to a first voltage source supplying a first voltage. The first node is charged to the first voltage by the transistor. One of electrodes of the first capacitor is connected to the first node, and the other of the electrodes of the first capacitor is supplied with a first clock signal having a second voltage. One end of the first switch is connected to the first node. The first switch outputs a potential of the first node at a first time at which the first switch is turned on. One end of the second switch is connected to the first node. The second switch outputs the potential of the first node at a second time.

摘要翻译： 根据一个实施例，半导体存储装置包括晶体管，第一节点，第一电容器，第一开关和第二开关。 晶体管的一端连接到提供第一电压的第一电压源。 第一个节点被晶体管充电到第一个电压。 第一电容器的电极中的一个连接到第一节点，并且第一电容器的另一个电极被提供有具有第二电压的第一时钟信号。 第一开关的一端连接到第一节点。 第一开关在第一开关被接通的第一时间输出第一节点的电位。 第二开关的一端连接到第一节点。 第二个开关在第二个时间输出第一个节点的电位。

公开(公告)号：US20120069668A1

公开(公告)日：2012-03-22

申请号：US13235426

申请日：2011-09-18

申请人： Kosuke HATSUDA

发明人： Kosuke HATSUDA

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/30

摘要： According to one embodiment, a semiconductor storage device includes a transistor, a first node, a first capacitor, a first switch, and a second switch. One end of the transistor is connected to a first voltage source supplying a first voltage. The first node is charged to the first voltage by the transistor. One of electrodes of the first capacitor is connected to the first node, and the other of the electrodes of the first capacitor is supplied with a first clock signal having a second voltage. One end of the first switch is connected to the first node. The first switch outputs a potential of the first node at a first time at which the first switch is turned on. One end of the second switch is connected to the first node. The second switch outputs the potential of the first node at a second time.

摘要翻译： 根据一个实施例，半导体存储装置包括晶体管，第一节点，第一电容器，第一开关和第二开关。 晶体管的一端连接到提供第一电压的第一电压源。 第一个节点被晶体管充电到第一个电压。 第一电容器的电极中的一个连接到第一节点，并且第一电容器的另一个电极被提供有具有第二电压的第一时钟信号。 第一开关的一端连接到第一节点。 第一开关在第一开关被接通的第一时间输出第一节点的电位。 第二开关的一端连接到第一节点。 第二个开关在第二个时间输出第一个节点的电位。

公开(公告)号：US20100153626A1

公开(公告)日：2010-06-17

申请号：US12529223

申请日：2009-02-10

申请人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda ,  Hiroki Matsudaira

发明人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda ,  Hiroki Matsudaira

IPC分类号： G06F12/00 ,  G06F12/16 ,  G06F12/02

CPC分类号： G06F11/1435 ,  G06F11/1441 ,  G06F11/1471 ,  G06F11/1474

摘要： To provide a memory system that can surely restore management information even when a program error occurs during data writing. After “log writing (1)” for a pre-log, when a program error occurs when data writing is being performed (a data writing error), the memory system performs the data writing again without acquiring a pre-log corresponding to data rewriting processing. After finishing the data writing, the memory system acquires, without generating a post-log, a snapshot instead of the post-log and finishes the processing.

摘要翻译： 提供即使在数据写入过程中发生程序错误时也可以确保还原管理信息的存储系统。 在“日志写入（1）”作为预登录之后，当执行数据写入时发生程序错误（数据写入错误）时，存储器系统再次执行数据写入，而不获取对应于数据重写的预记录 处理。 在完成数据写入之后，内存系统在不生成后记录的情况下获取快照而不是后记录，并完成处理。

公开(公告)号：US20100107021A1

公开(公告)日：2010-04-29

申请号：US12523607

申请日：2008-09-30

申请人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda

发明人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda

IPC分类号： G11C29/52 ,  G06F11/10

CPC分类号： G11C16/349 ,  G06F11/1068 ,  G11C11/005 ,  G11C16/3431

摘要： This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

摘要翻译： 本公开涉及存储器，包括：包括存储器组的第一存储器区域，包括多个存储器单元，分别分配给存储器组的地址，存储器组分别是数据擦除操作的单位; 第二存储器区域暂时存储从第一存储器区域读取的数据或者暂时存储要写入到第一存储器区域的数据; 读取计数器，存储每个存储器组的数据读取计数; 错误校正电路，计算读取数据的错误位数; 以及执行刷新操作的控制器，其中存储在一个存储器组中的读取数据被临时存储在第二存储器区域中，并且当读取数据写入同一存储器组时，当错误位计数超过第一阈值时 或者当数据读取计数超过第二阈值时。

公开(公告)号：US07277341B2

公开(公告)日：2007-10-02

申请号：US11444487

申请日：2006-06-01

申请人： Katsuyuki Fujita ,  Kosuke Hatsuda ,  Takashi Ohsawa

发明人： Katsuyuki Fujita ,  Kosuke Hatsuda ,  Takashi Ohsawa

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C11/406 ,  G11C2211/4016 ,  G11C2211/4065

摘要： A semiconductor memory device has first and second sense nodes which are provided corresponding to first and second bit lines, and a sense amplifier which is connected to the first and second sense nodes and senses data read out from a memory cell, wherein the sense amplifier includes an initial sense circuit which increases a potential difference between the first and second sense nodes in a first period after beginning sense operation, and a latch circuit which increases and holds the potential difference between the first and second sense nodes in a second period after the first period, wherein the initial sense circuit includes first and second transistors of first conductive type, third and fourth transistors of first conductive type, and fifth and sixth transistors of first conductive type, wherein the latch circuit includes seventh and eighth transistors of first conductive type, and ninth and tenth transistors of second conductive type.

摘要翻译： 半导体存储器件具有对应于第一和第二位线提供的第一和第二感测节点，以及连接到第一和第二感测节点并感测从存储器单元读出的数据的读出放大器，其中读出放大器包括 初始感测电路，其在开始感测操作之后的第一周期中增加第一和第二感测节点之间的电位差;以及锁存电路，其在第一和第二感测节点之后的第二周期中增加并保持第一和第二感测节点之间的电位差 周期，其中所述初始检测电路包括第一导电类型的第一和第二晶体管，第一导电类型的第三和第四晶体管，以及第一导电类型的第五和第六晶体管，其中所述锁存电路包括第一和第八晶体管， 以及第二导电类型的第九和第十晶体管。

公开(公告)号：US08745313B2

公开(公告)日：2014-06-03

申请号：US12394632

申请日：2009-02-27

申请人： Junji Yano ,  Kosuke Hatsuda ,  Hidenori Matsuzaki ,  Wataru Okamoto

发明人： Junji Yano ,  Kosuke Hatsuda ,  Hidenori Matsuzaki ,  Wataru Okamoto

IPC分类号： G06F12/00

CPC分类号： G06F3/061 ,  G06F3/065 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2206/1014 ,  G06F2212/7203 ,  G06F2212/7205 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/102 ,  G11C2211/5643 ,  G11C2211/5646

摘要： A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management tablet the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated.

摘要翻译： 存储器系统包括具有块的非易失性半导体存储器，该块是数据擦除单元; 以及控制器，被配置为执行; 更新处理; 在块中写入替代数据，替代数据被视为有效数据; 并且使具有与取代数据相同的逻辑地址的替代数据无效，所取代的数据被视为无效数据; 和压实处理; 使用管理数据库检索具有无效数据的块，所述管理表管理所述块中包括的每个数量的有效数据的链接列表格式的块; 从所检索的块中选择具有至少一个有效数据的压缩源块; 将压缩源块中包括的多个有效数据复制到压缩目标块中; 使压缩源块中的多个有效数据无效; 并释放其中所有数据无效的压缩源块。

公开(公告)号：US08650373B2

公开(公告)日：2014-02-11

申请号：US12860160

申请日：2010-08-20

申请人： Kosuke Hatsuda ,  Daisaburo Takashima

发明人： Kosuke Hatsuda ,  Daisaburo Takashima

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F11/1441

摘要： According to one embodiment, a memory system includes a nonvolatile first memory, a nonvolatile second memory, a data-copy processing unit and a data invalidation processing unit. The first memory has a storage capacity for n (n≧2) pages per word line. The nonvolatile second memory temporarily stores user data write-requested from a host apparatus. The data-copy processing unit executes data copy processing including reading out, in page units, the user data stored in the second memory and sequentially writing the read-out user data in page units in the first memory. The data invalidation processing unit selects, after the execution of the data copy processing, based on whether the memory cell group per word line stores user data for n pages, user data requiring backup out of the user data subjected to the data copy processing and leaves the selected user data in the second memory as backup data.

摘要翻译： 根据一个实施例，存储器系统包括非易失性第一存储器，非易失性第二存储器，数据复制处理单元和数据无效化处理单元。 第一个存储器具有每个字线n（n> = 2）页的存储容量。 非易失性第二存储器临时存储从主机装置写入请求的用户数据。 数据复制处理单元执行数据复制处理，包括以页为单位读出存储在第二存储器中的用户数据，并以页单元顺序地将读出的用户数据写入第一存储器。 数据无效处理单元在执行数据复制处理之后，根据每个字线的存储单元组是否存储n页的用户数据，选择需要备份的用户数据进行数据复制处理的用户数据，并且离开 所选择的用户数据在第二存储器中作为备份数据。

公开(公告)号：US08554984B2

公开(公告)日：2013-10-08

申请号：US12529127

申请日：2009-02-10

申请人： Junji Yano ,  Kosuke Hatsuda ,  Hidenori Matsuzaki

发明人： Junji Yano ,  Kosuke Hatsuda ,  Hidenori Matsuzaki

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/7201 ,  G06F2212/7209

摘要： A memory system in which speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponds to the logical address, and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position. These forward and reverse lookup tables are linked.

摘要翻译： 通过提供从逻辑地址，数据对应于逻辑地址的存储设备位置分别在轨道和群集单元中搜索的前向查找表来增加用于通过管理表搜索的处理速度的存储器系统，以及 用于从存储设备的位置搜索存储在该位置中的逻辑地址的反向查找表。 这些正向和反向查找表是链接的。

公开(公告)号：US08443133B2

公开(公告)日：2013-05-14

申请号：US12529145

申请日：2009-02-10

申请人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

发明人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

IPC分类号： G06F12/00

CPC分类号： G06F3/0619 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0685 ,  G06F11/1456 ,  G06F11/1469 ,  G06F11/1471 ,  G06F12/0246 ,  G06F2201/84 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C7/20 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/105

摘要： A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

公开(公告)号：US08429333B2

公开(公告)日：2013-04-23

申请号：US12394582

申请日：2009-02-27

申请人： Junji Yano ,  Kosuke Hatsuda ,  Hidenori Matsuzaki

发明人： Junji Yano ,  Kosuke Hatsuda ,  Hidenori Matsuzaki

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/7201

摘要： A controller includes an identification information management table that manages identification information indicating, for each of addresses in second-management unit, whether one or more data in first management unit belonging to the addresses is stored in the second or the third storing area. When the controller executes a process of flushing data from the first storing area to the second storing area or the third storing area, the controller updates the identification information in the identification information management table. The controller executes a process of reading data from the second storing area or the third storing area by referring to the identification information. As a result, the speed of searches conducted in the management table is increased.