公开(公告)号：US20140065789A1

公开(公告)日：2014-03-06

申请号：US14076261

申请日：2013-11-10

Applicant: Hitachi, Ltd.

Inventor： Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Mitsuharu TAI ,  Takashi KOBAYASHI

IPC: H01L27/24

CPC classification number: H01L27/2481 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472

Abstract: In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.

Abstract translation: 在非易失性半导体存储器件中，提供了一种通过减小作为选择元件的多晶硅二极管的截止电流来减小器件厚度来促进微细加工的技术。 形成以低浓度掺杂有杂质并作为电阻可变存储器的选择元件的多晶硅二极管的电场弛豫层的多晶硅层，以被分成两层或多层，例如多晶硅 层。 以这种方式抑制电场弛豫层中的n型多晶硅层和p型多晶硅层之间的晶粒边界完全穿透，从而防止产生流过的漏电流 在不增加多晶硅二极管的高度的情况下施加反偏压的晶界。

公开(公告)号：US20170040379A1

公开(公告)日：2017-02-09

申请号：US15106133

申请日：2013-12-27

Applicant: HITACHI, LTD.

Inventor： Yoshitaka SASAGO ,  Hiroshi YOSHITAKE ,  Koji FUJISAKI ,  Takashi KOBAYASHI ,  Makoto KUDO

IPC: H01L27/24 ,  H01L23/528

CPC classification number: H01L27/249 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/75 ,  H01L21/823487 ,  H01L23/528 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/144

Abstract: An object of the present invention is to reduce a pitch of selection transistors to select two directions in a semiconductor substrate surface of a three-dimensional vertical semiconductor storage device to reduce a dimension in the semiconductor substrate surface.Gates of selection transistors extending in the same direction are formed by a different process for every other gate, so that the thickness of channel semiconductor layers of the selection transistors can be reduced to almost the same thickness of the thickness of an inversion layer while the channel semiconductor layers and an electrode are contacted over a wide area. On/off control can be executed independently on the channel semiconductor layers formed at two sidewalls of the gates of the selection transistors formed at a pitch of 2F. As a result, dimensions of two directions in the semiconductor substrate surface can be set to 2F without generating double selection.

Abstract translation: 在相同方向上延伸的选择晶体管的栅极通过对于每隔一个栅极的不同处理形成，使得选择晶体管的沟道半导体层的厚度可以减小到反转层的厚度的几乎相同的厚度，而沟道 半导体层和电极在大面积上接触。 可以在以2F的间距形成的选择晶体管的两个侧壁的形成的沟道半导体层上独立地执行开/关控制。 结果，可以将半导体衬底表面中的两个方向的尺寸设置为2F而不产生双重选择。

公开(公告)号：US20150118804A1

公开(公告)日：2015-04-30

申请号：US14506661

申请日：2014-10-05

Applicant: Hitachi, Ltd.

Inventor： Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Takahiro MORIKAWA ,  Akio SHIMA ,  Takashi KOBAYASHI

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/66833 ,  H01L29/7926 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1683

Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.

Abstract translation: 垂直链式存储器包括具有第一选择晶体管的两层选择晶体管，它们是以矩阵形式排列的垂直晶体管，第二选择晶体管是形成在各个第一选择晶体管上的垂直晶体管，以及多个存储单元串联连接 两层选择晶体管。 利用这种配置，防止相邻的选择晶体管被相应的共享栅极选择，可以独立地选择多个两层选择晶体管，并且防止非易失性存储装置的存储容量减小。

公开(公告)号：US20170125675A1

公开(公告)日：2017-05-04

申请号：US15128395

申请日：2014-03-28

Applicant: HITACHI, LTD.

Inventor： Yoshihisa FUJISAKI ,  Yoshitaka SASAGO ,  Takashi KOBAYASHI

IPC: H01L45/00 ,  C23C16/448 ,  C23C16/22

CPC classification number: H01L45/1616 ,  C23C16/22 ,  C23C16/4482 ,  C23C16/452 ,  C23C16/45561 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: In order to form a phase change thin film being flat in a nanometer level and having a good coverage, which is essential for realizing a three-dimensional ultra-high integrated phase change memory, an equipment for vapor phase growth of a phase change thin film is provided which form a phase change thin film at low temperature while the film is being kept in a completely amorphous state. A structure is provided in which an ammonia cracker is connected to a reactor of the equipment for vapor phase growth for a nitrogen radical obtained by decomposing ammonia gas. Consequently, low temperature decomposition of metal organic precursor and film formation on a substrate surface are realized. With the use of this equipment, it is possible to realize a completely amorphous film which has a flat surface at a low temperature of 135° C. using an amine complex as a Ge precursor.

公开(公告)号：US20160079529A1

公开(公告)日：2016-03-17

申请号：US14860349

申请日：2015-09-21

Applicant: Hitachi, Ltd.

Inventor： Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Mitsuharu TAI ,  Akio SHIMA ,  Kenzo KUROTSUCHI ,  Takashi KOBAYASHI

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  G11C13/0004 ,  G11C2213/75 ,  H01L27/0688 ,  H01L27/1021 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/7926 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

Abstract: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.