公开(公告)号：US20180350973A1

公开(公告)日：2018-12-06

申请号：US15759790

申请日：2015-09-15

Applicant: Hitachi, Ltd.

Inventor： Yuki MORI ,  Akio SHIMA

IPC: H01L29/78 ,  H02P27/06 ,  H01L29/16 ,  H01L29/167 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/04 ,  B60L15/00

CPC classification number: H01L29/7811 ,  B60L15/00 ,  B60L2200/26 ,  H01L21/0465 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7805 ,  H01L29/861 ,  H01L29/868 ,  H02P27/06

Abstract: An object of the present invention is to suppress energization deterioration due to crystal defects in a semiconductor device including SiC-MOSFET. To solve this problem, a semiconductor device of the present invention includes: an n−-type epitaxial layer formed on a main surface of an n+-type SiC substrate; a p-type termination region that is annularly formed in the n−-type epitaxial layer outside an active region; and an n-type hole annihilation region annularly formed in the n−-type epitaxial layer outside the p-type termination region, apart from the p-type termination region. Then, the n-type hole annihilation region has a first end surface facing the p-type termination region, as well as a second end surface on the opposite side of the first end surface. When a depth of the n-type hole annihilation region is dTM, a depth of the p-type termination region is dNR, a thickness of the n−-type epitaxial layer is dEpi, a distance from the first end surface of the n-type hole annihilation region to the second end surface thereof is LNR, and a distance from the first end surface of the n-type hole annihilation region to the periphery of the semiconductor substrate is |XNR|, these variables have the following relationship: dNR≤dTM, (|XNR|+dNR)≥dEpi, 0

公开(公告)号：US20180059263A1

公开(公告)日：2018-03-01

申请号：US15556789

申请日：2015-07-06

Applicant: HITACHI, LTD.

Inventor： Norifumi KAMESHIRO ,  Akio SHIMA

IPC: G01T1/24 ,  H01L31/0312 ,  H01L31/115 ,  H01L31/02 ,  H01L31/0224

CPC classification number: G01T1/241 ,  G01T1/24 ,  H01L31/02019 ,  H01L31/022408 ,  H01L31/0312 ,  H01L31/115 ,  H01L31/117

Abstract: There is provided a radiation detector using SiC and of a structure in which an electric field is applied to the interior of the entire SiC crystal constituting a radiation sensible layer, aiming to detect radiation while suppressing a reduction in electric signals generated in the radiation sensible layer.The radiation detector includes: a radiation sensible layer formed of silicon carbide and configured to generate an electron hole pair due to radiation entering it; a first semiconductor region in contact with a first principal surface of the radiation sensible layer and exhibiting a first impurity concentration at least in the region in contact with the radiation sensible layer; a second semiconductor region in contact with a second principal surface on the opposite side of the first principal surface and exhibiting a second impurity concentration at least in the region in contact with the radiation sensible layer; a first electrode connected to the first semiconductor region; and a second electrode connected to the second semiconductor region. The impurity concentration in the radiation sensible layer adjacent to the first semiconductor region, with the first principal surface serving as a border, is discontinuous with the first impurity concentration; the impurity concentration in the radiation sensible layer adjacent to the second semiconductor region, with the second principal surface serving as a border, is discontinuous with the second impurity concentration; and an electric field is applied to the entire radiation sensible layer in the depth direction thereof at a voltage during operation.

公开(公告)号：US20190326393A1

公开(公告)日：2019-10-24

申请号：US16265455

申请日：2019-02-01

Applicant: HITACHI, LTD.

Inventor： Masahiro MASUNAGA ,  Akio SHIMA ,  Shintaroh SATO ,  Ryo KUWANA

IPC: H01L29/06 ,  H01L29/08 ,  H01L23/535 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66 ,  H01L29/16 ,  H01L29/45

Abstract: A MOSFET that has a drain region and a source region on an upper surface of a semiconductor substrate and a gate electrode that is formed on the semiconductor substrate, and an element separation insulating film that includes an opening portion which exposes an active region, on the semiconductor substrate, are formed. At this point, a gate leading-out interconnection that overlaps the element separation insulating film when viewed from above, and that is integrally combined with the gate electrode is formed in a position where the gate leading-out interconnection does not extend over a distance between both the drain region and the source region when viewed from above, on a region that is exposed from the gate electrode.

公开(公告)号：US20190115465A1

公开(公告)日：2019-04-18

申请号：US16025656

申请日：2018-07-02

Applicant: HITACHI, LTD.

Inventor： Kumiko KONISHI ,  Ryuusei FUJITA ,  Kazuki TANI ,  Akio SHIMA

IPC: H01L29/78 ,  H01L29/16

CPC classification number: H01L29/7805 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

Abstract: Provided is a silicon carbide semiconductor device in which SiC-MOSFETs are formed within an active region of an n-type silicon carbide semiconductor substrate, and a p+-type semiconductor region is formed on an upper surface of an epitaxial layer so as to surround the active region.

公开(公告)号：US20190198495A1

公开(公告)日：2019-06-27

申请号：US16217398

申请日：2018-12-12

Applicant: HITACHI, LTD.

Inventor： Ryuusei FUJITA ,  Kumiko KONISHI ,  Akio SHIMA

IPC: H01L27/06 ,  H03K17/082 ,  H01L29/423 ,  H01L27/02

Abstract: An object of the present invention is to increase the reliability of a power module and a power converter and to extend their life. In order to achieve this, a power module includes: two switching devices each including a diode and a transistor, the two switching devices being electrically connected in parallel; and an insulating substrate on which the two switching devices are mounted. Further, a gate electrode of MOFET that each of the two switching device has is electrically connected to a gate resistance. Further, of the two switching devices, the gate resistance that is electrically connected to the switching device, whose current value is smaller when a predetermined voltage is applied in the forward direction of the body diode, is greater than the gate resistance that is electrically connected to the switching device whose current value is larger.

公开(公告)号：US20180026009A1

公开(公告)日：2018-01-25

申请号：US15527089

申请日：2015-03-13

Applicant: HITACHI, LTD.

Inventor： Ryuusei FUJITA ,  Satoru AKIYAMA ,  Hiroshi KAGEYAMA ,  Toru MASUDA ,  Ayumu HATANAKA ,  Akio SHIMA

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/467 ,  H02P27/06 ,  B60L11/18 ,  H02M7/00 ,  H01L27/06

CPC classification number: H01L25/0655 ,  B60L11/1803 ,  B60L11/1812 ,  B60L15/007 ,  H01L23/467 ,  H01L23/49844 ,  H01L25/00 ,  H01L27/0629 ,  H01L2224/0603 ,  H01L2224/49111 ,  H01L2224/49113 ,  H02M7/003 ,  H02P27/06

Abstract: The object of the present invention is to compensate for a difference in threshold voltage between a plurality of switching devices incorporated in a power module.The present invention solves the subject described above by mounting a switching device having a high threshold voltage in comparison with a different switching device at a location at which the temperature of the power module during operation is higher than that at another location at which the different switching device is mounted. Eventually, a power conversion apparatus of a high performance and a vehicle drive apparatus of a high performance can be provided.

公开(公告)号：US20150118804A1

公开(公告)日：2015-04-30

申请号：US14506661

申请日：2014-10-05

Applicant: Hitachi, Ltd.

Inventor： Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Takahiro MORIKAWA ,  Akio SHIMA ,  Takashi KOBAYASHI

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/66833 ,  H01L29/7926 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1683

Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.

Abstract translation: 垂直链式存储器包括具有第一选择晶体管的两层选择晶体管，它们是以矩阵形式排列的垂直晶体管，第二选择晶体管是形成在各个第一选择晶体管上的垂直晶体管，以及多个存储单元串联连接 两层选择晶体管。 利用这种配置，防止相邻的选择晶体管被相应的共享栅极选择，可以独立地选择多个两层选择晶体管，并且防止非易失性存储装置的存储容量减小。

公开(公告)号：US20190319103A1

公开(公告)日：2019-10-17

申请号：US16462319

申请日：2017-10-24

Applicant: HITACHI, LTD.

Inventor： Masahiro MASUNAGA ,  Shintaroh SATO ,  Akio SHIMA ,  Digh HISAMOTO

IPC: H01L29/16 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36 ,  H01L27/02 ,  H01L29/417 ,  H01L23/498 ,  H01L23/00 ,  H01L21/02 ,  H01L21/82 ,  H01L29/66

Abstract: The purpose of the present invention is to provide a semiconductor device comprising an epitaxial layer formed on a SiC substrate, and a CMOS formed in the top part of the epitaxial layer, wherein growth of any defects present at the interface between the SiC substrate and the epitaxial layer is suppressed, and the reliability of the semiconductor device is improved. As a means to achieve the foregoing, a semiconductor device is formed such that the distance from a p-type diffusion layer to the interface between an n-type epitaxial layer and an n-type semiconductor substrate is larger than the thickness of a depletion layer that extends from the p-type diffusion layer to the back side of the n-type semiconductor substrate in response to the potential difference between a substrate electrode and another substrate electrode.

公开(公告)号：US20160284690A1

公开(公告)日：2016-09-29

申请号：US14914883

申请日：2013-08-29

Applicant: HITACHI, LTD.

Inventor： Hiroyuki YOSHIMOTO ,  Akio SHIMA ,  Digh HISAMOTO

IPC: H01L27/06 ,  H01L29/66 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/36 ,  H01L29/739 ,  H01L29/10

CPC classification number: H01L27/0623 ,  H01L21/2253 ,  H01L21/8249 ,  H01L29/0619 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/78

Abstract: An IGBT (50) includes a p+ collector region (3) and an n−− drift region (1), in which a first transistor (TR1) and a second transistor (TR2) are formed on the n−− drift region (1). In the n−− drift region (1), a p-type hole extraction region (14) is formed in contact with the second transistor (TR2). When the IGBT (50) is in an on-state, electrons and holes flow through the first transistor (TR1), but a current does not flow through the second transistor (TR2). On the other hand, when the IGBT (50) is switched from the on-state to an off-state, holes flow through the first transistor (TR1), and holes flow through the hole extraction region (14) and the second transistor (TR2).

Abstract translation: IGBT（50）包括p +集电极区（3）和n漂移区（1），其中在漂移区（1）上形成第一晶体管（TR1）和第二晶体管（TR2） ）。 在n漂移区域（1）中，形成与第二晶体管（TR2）接触的p型空穴提取区域（14）。 当IGBT（50）处于导通状态时，电子和空穴流过第一晶体管（TR1），但电流不流过第二晶体管（TR2）。 另一方面，当IGBT（50）从导通状态切换到断开状态时，空穴流过第一晶体管（TR1），空穴流过空穴取出区域（14）和第二晶体管（ TR2）。

公开(公告)号：US20160079529A1

公开(公告)日：2016-03-17

申请号：US14860349

申请日：2015-09-21

Applicant: Hitachi, Ltd.

Inventor： Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Mitsuharu TAI ,  Akio SHIMA ,  Kenzo KUROTSUCHI ,  Takashi KOBAYASHI

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  G11C13/0004 ,  G11C2213/75 ,  H01L27/0688 ,  H01L27/1021 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/7926 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

Abstract: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.