公开(公告)号：US20170373599A1

公开(公告)日：2017-12-28

申请号：US15699274

申请日：2017-09-08

Applicant: HITACHI, LTD.

Inventor： Takayuki HASHIMOTO ,  Mutsuhiro MORI

IPC: H02M3/158 ,  H02M1/32 ,  H03K17/082 ,  H01L29/786 ,  H02M1/00 ,  H03K17/16

CPC classification number: H02M3/158 ,  H01L29/786 ,  H02M1/00 ,  H02M1/32 ,  H02M2001/0009 ,  H03K17/0828 ,  H03K17/168 ,  H03K2217/0036

Abstract: An apparatus is adapted to drive an insulating gate-type semiconductor element by a first control voltage and a second control voltage, that are supplied to a first insulating gate and a second insulating gate, respectively, and includes a first noise filter inputting a signal about current that passes through the insulating gate-type semiconductor element, a first comparator making a comparison between an output signal of the first noise filter and a first reference signal and outputting a first comparison result, a first control voltage output circuit, and a second control voltage output circuit, the second control voltage output circuit being adapted to reduce the second control voltage when it is determined from the first comparison result that overcurrent passes through the insulating gate-type semiconductor element, the first control voltage output circuit being adapted to reduce the first control voltage after the second control voltage is reduced.

公开(公告)号：US20160013300A1

公开(公告)日：2016-01-14

申请号：US14770448

申请日：2013-02-25

Applicant: HITACHI, LTD.

Inventor： Takayuki HASHIMOTO ,  Mutsuhiro MORI

IPC: H01L29/739 ,  H01L29/36 ,  H02M7/537 ,  H01L29/423

CPC classification number: H01L29/7391 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/7393 ,  H01L29/7813 ,  H02M7/537 ,  H03K2017/307

Abstract: A semiconductor device according to the present invention includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type adjacent to the first semiconductor layer and having an impurity concentration lower than the first semiconductor layer; a third semiconductor layer of a second conductivity type adjacent to the second semiconductor layer; a fourth semiconductor layer of the first conductivity type located within the third semiconductor layer; a first electrode coupled to the third semiconductor layer and the fourth semiconductor layer; a second electrode coupled to the first semiconductor layer; and an insulated gate provided over the respective surfaces of the third semiconductor layer and the fourth semiconductor layer, wherein peak value of the impurity concentration of the third semiconductor layer is in the range of 2×1016 cm−3 or more and 5×1018 cm−3 or less.

Abstract translation: 根据本发明的半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层，与第一半导体层相邻，杂质浓度低于第一半导体层; 与第二半导体层相邻的第二导电类型的第三半导体层; 位于第三半导体层内的第一导电类型的第四半导体层; 耦合到所述第三半导体层和所述第四半导体层的第一电极; 耦合到所述第一半导体层的第二电极; 以及设置在所述第三半导体层和所述第四半导体层的各个表面上的绝缘栅极，其中所述第三半导体层的杂质浓度的峰值在2×10 16 cm -3以上且5×10 18 cm的范围内 -3以下。

公开(公告)号：US20160013299A1

公开(公告)日：2016-01-14

申请号：US14770443

申请日：2013-02-25

Applicant: HITACHI, LTD.

Inventor： Takayuki HASHIMOTO ,  Mutsuhiro MORI

IPC: H01L29/739 ,  H01L29/36 ,  H02M7/53 ,  H01L29/423

CPC classification number: H01L29/7391 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/7393 ,  H02M7/53 ,  H03K2017/307

Abstract: A semiconductor device according to the present invention includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type, which is adjacent to the first semiconductor layer and has an impurity concentration lower than the first semiconductor layer; a third semiconductor layer adjacent to the second semiconductor layer; a first electrode electrically coupled to the third semiconductor layer; a second electrode electrically coupled to the first semiconductor layer; and an insulated gate provided over the surface of the third semiconductor layer. Then, an end portion of the insulated gate is located at a position distant from the junction part between the second semiconductor layer and the third semiconductor layer within the surface of the third semiconductor layer.

Abstract translation: 根据本发明的半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层，其与第一半导体层相邻并且具有低于第一半导体层的杂质浓度; 与所述第二半导体层相邻的第三半导体层; 电耦合到所述第三半导体层的第一电极; 电耦合到所述第一半导体层的第二电极; 以及设置在第三半导体层的表面上的绝缘栅极。 然后，绝缘栅极的端部位于远离第三半导体层的表面内的第二半导体层和第三半导体层之间的接合部的位置。

公开(公告)号：US20240285972A1

公开(公告)日：2024-08-29

申请号：US18375597

申请日：2023-10-02

Applicant: Hitachi, Ltd. ,  NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY

Inventor： Taisuke TAKAYANAGI ,  Takahiro YAMADA ,  Shusuke HIRAYAMA ,  Koichi MIYAZAKI ,  Keiji KOBASHI ,  Hidefumi AOYAMA ,  Takayuki HASHIMOTO ,  Norio KATOH ,  Hiroshi TAGUCHI ,  Koichi YASUDA ,  Yasuhito ONODERA

IPC: A61N5/10

CPC classification number: A61N5/1038 ,  A61N5/1064 ,  A61N2005/1092

Abstract: A treatment planning system is configured to create a treatment planning for radiotherapy and includes a processing device and a memory. The memory stores a plurality of calculation models, and the processing device uses at least two of the plurality of calculation models to calculate calculation values of biological effect indices representing an effect of radiotherapy with respect to a condition for radiotherapy, and searches for the condition so that at least two of the calculation values to be calculated approach a predetermined target value.

公开(公告)号：US20170141677A1

公开(公告)日：2017-05-18

申请号：US15420393

申请日：2017-01-31

Applicant: Hitachi, Ltd.

Inventor： Takayuki HASHIMOTO ,  Mutsuhiro MORI ,  Masahiro MASUNAGA

IPC: H02M1/088 ,  H01L29/10 ,  H02M7/5387 ,  H01L29/417 ,  H01L29/739 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08

CPC classification number: H02M1/088 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1079 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7394 ,  H01L29/7396 ,  H01L29/7397 ,  H02M1/08 ,  H02M7/003 ,  H02M7/537 ,  H02M7/5387 ,  H02M2001/0054

Abstract: The present invention provides a switching device (100) for power conversion in which a first gate electrode (6), a p-type channel layer (2) having an n-type emitter region (3), a second gate electrode (13), and a p-type floating layer (15) are repeatedly arranged in order on the surface side of an n−type semiconductor substrate (1). An interval a between the two gates (6, 13) that sandwich the p-type channel layer (2) is configured to be smaller than an interval b between the two gates (13, 6) that sandwich the p-type floating layer (15). The first gate electrode (6) and the second gate electrode (13) are both supplied with drive signals having a time difference in drive timing.

公开(公告)号：US20160343838A1

公开(公告)日：2016-11-24

申请号：US15114513

申请日：2014-01-31

Applicant: HITACHI, LTD.

Inventor： Takayuki HASHIMOTO

IPC: H01L29/739 ,  H02M7/00 ,  H02M7/44 ,  H01L27/06

CPC classification number: H01L29/7391 ,  H01L27/0664 ,  H01L29/083 ,  H01L29/0847 ,  H01L29/7397 ,  H02M7/003 ,  H02M7/44 ,  H03K17/162 ,  H03K17/74 ,  H03K2217/0036

Abstract: This semiconductor element drive apparatus switches an insulating gate at a positive voltage to at a negative voltage just before recovery when an anode current is large, and holds the insulating gate at the positive voltage when the anode current is small in a semiconductor element that is provided with: a first conductivity type first semiconductor layer (n− type drift layer); a second conductivity type second semiconductor layer (p type anode layer) that is adjacent to the first semiconductor layer and is exposed on one main surface (anode side); a first conductivity type third semiconductor layer (n type cathode layer) that is adjacent to the first semiconductor layer, is exposed on the other main surface (cathode side), and has an impurity concentration higher than that of the first semiconductor layer (n− type drift layer); and the insulating gate on the other main surface (cathode side).

Abstract translation: 该半导体元件驱动装置在阳极电流较大时刚好在恢复之前将正电压的绝缘栅极切换到负电压，并且在设置的半导体元件中的阳极电流较小时将绝缘栅极保持为正电压 具有：第一导电型第一半导体层（n-型漂移层）; 与第一半导体层相邻并暴露在一个主表面（阳极侧）的第二导电型第二半导体层（p型阳极层）; 与第一半导体层相邻的第一导电型第三半导体层（n型阴极层）在另一主面（阴极侧）露出，杂质浓度高于第一半导体层（n型阴极层） 型漂移层）; 和另一个主表面（阴极侧）上的绝缘栅极。

公开(公告)号：US20160118891A1

公开(公告)日：2016-04-28

申请号：US14889850

申请日：2013-05-10

Applicant: HITACHI, LTD.

Inventor： Takayuki HASHIMOTO ,  Mutsuhiro MORI

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H01L29/786 ,  H02M1/00 ,  H02M1/32 ,  H02M2001/0009 ,  H03K17/0828 ,  H03K17/168 ,  H03K2217/0036

Abstract: An apparatus is adapted to drive an insulating gate-type semiconductor element by a first control voltage and a second control voltage, that are supplied to a first insulating gate and a second insulating gate, respectively, and includes a first noise filter inputting a signal about current that passes through the insulating gate-type semiconductor element, a first comparator making a comparison between an output signal of the first noise filter and a first reference signal and outputting a first comparison result, a first control voltage output circuit, and a second control voltage output circuit, the second control voltage output circuit being adapted to reduce the second control voltage when it is determined from the first comparison result that overcurrent passes through the insulating gate-type semiconductor element, the first control voltage output circuit being adapted to reduce the first control voltage after the second control voltage is reduced.

Abstract translation: 一种装置适于通过分别提供给第一绝缘栅极和第二绝缘栅极的第一控制电压和第二控制电压来驱动绝缘栅型半导体元件，并且包括第一噪声滤波器，其输入关于 通过绝缘栅型半导体元件的电流;第一比较器，对第一噪声滤波器的输出信号和第一参考信号进行比较，并输出第一比较结果，第一控制电压输出电路和第二控制 电压输出电路，当从第一比较结果确定过电流通过绝缘栅型半导体元件确定第二控制电压输出电路时，第二控制电压输出电路适于减小第二控制电压，第一控制电压输出电路适于减少 第二控制电压降低后的第一控制电压。