公开(公告)号：US20170236768A1

公开(公告)日：2017-08-17

申请号：US15501374

申请日：2015-09-09

Applicant: HITACHI, LTD.

Inventor： Takashi NAITO ,  Motomune KODAMA ,  Takuya AOYAGI ,  Shigeru KIKUCHI ,  Takashi NOGAWA ,  Mutsuhiro MORI ,  Eiichi IDE ,  Toshiaki MORITA ,  Akitoyo KONNO ,  Taigo ONODERA ,  Tatsuya MIYAKE ,  Akihiko MIYAUCHI

IPC: H01L23/373 ,  H01L23/00 ,  C03C8/02 ,  C03C8/24 ,  C03C8/08

CPC classification number: H01L23/3733 ,  C03C3/122 ,  C03C3/125 ,  C03C3/21 ,  C03C8/02 ,  C03C8/08 ,  C03C8/18 ,  C03C8/24 ,  C09J1/00 ,  C09J11/04 ,  H01L21/52 ,  H01L23/3731 ,  H01L23/3735 ,  H01L24/29 ,  H01L25/07 ,  H01L25/18 ,  H01L2224/29211 ,  H01L2224/29224 ,  H01L2224/29239 ,  H01L2224/29247 ,  H01L2224/29287 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: A heat-dissipating structure is formed by bonding a first member and a second member, each being any of a metal, ceramic, and semiconductor, via a die bonding member; or a semiconductor module formed by bonding a semiconductor chip, a metal wire, a ceramic insulating substrate, and a heat-dissipating base substrate including metal, with a die bonding member interposed between each. At least one of the die bonding members includes a lead-free low-melting-point glass composition and metal particles. The lead-free low-melting-point glass composition accounts for 78 mol % or more in terms of the total of the oxides V2O5, TeO2, and Ag2O serving as main ingredients. The content of each of TeO2 and Ag2O is 1 to 2 times the content of V2O5, and at least one of BaO, WO3, and P2O5 is included as accessory ingredients, and at least one of Y2O3, La2O3, and Al2O3 is included as additional ingredients.

公开(公告)号：US20160118891A1

公开(公告)日：2016-04-28

申请号：US14889850

申请日：2013-05-10

Applicant: HITACHI, LTD.

Inventor： Takayuki HASHIMOTO ,  Mutsuhiro MORI

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H01L29/786 ,  H02M1/00 ,  H02M1/32 ,  H02M2001/0009 ,  H03K17/0828 ,  H03K17/168 ,  H03K2217/0036

Abstract: An apparatus is adapted to drive an insulating gate-type semiconductor element by a first control voltage and a second control voltage, that are supplied to a first insulating gate and a second insulating gate, respectively, and includes a first noise filter inputting a signal about current that passes through the insulating gate-type semiconductor element, a first comparator making a comparison between an output signal of the first noise filter and a first reference signal and outputting a first comparison result, a first control voltage output circuit, and a second control voltage output circuit, the second control voltage output circuit being adapted to reduce the second control voltage when it is determined from the first comparison result that overcurrent passes through the insulating gate-type semiconductor element, the first control voltage output circuit being adapted to reduce the first control voltage after the second control voltage is reduced.

Abstract translation: 一种装置适于通过分别提供给第一绝缘栅极和第二绝缘栅极的第一控制电压和第二控制电压来驱动绝缘栅型半导体元件，并且包括第一噪声滤波器，其输入关于 通过绝缘栅型半导体元件的电流;第一比较器，对第一噪声滤波器的输出信号和第一参考信号进行比较，并输出第一比较结果，第一控制电压输出电路和第二控制 电压输出电路，当从第一比较结果确定过电流通过绝缘栅型半导体元件确定第二控制电压输出电路时，第二控制电压输出电路适于减小第二控制电压，第一控制电压输出电路适于减少 第二控制电压降低后的第一控制电压。

公开(公告)号：US20140001512A1

公开(公告)日：2014-01-02

申请号：US14015213

申请日：2013-08-30

Applicant: Hitachi, Ltd.

Inventor： So WATANABE ,  Mutsuhiro MORI ,  Taiga ARAI

IPC: H01L29/739

CPC classification number: H01L29/7395 ,  H01L21/2815 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor device provides a gate electrode formed on a lateral face of a wide trench, and thereby the gate electrode is covered by a gate insulating layer and a thick insulating layer to be an inter layer. Therefore, a parasitic capacitance of the gate becomes small, and there is no potential variation of the gate since there is no floating p-layer so that a controllability of the dv/dt can be improved. In addition, the conductive layer between the gate electrodes can relax the electric field applied to the corner of the gate electrode. In consequence, compatibility of low loss and low noise and high reliability can be achieved.

Abstract translation: 半导体器件提供形成在宽沟槽的侧面上的栅电极，由此栅电极被栅绝缘层和厚绝缘层覆盖为内层。 因此，栅极的寄生电容变小，并且由于不存在浮置p层而不具有栅极的电位变化，因此能够提高dv / dt的可控性。 此外，栅电极之间的导电层可以放宽施加到栅电极的角部的电场。 因此，可以实现低损耗和低噪声以及高可靠性的兼容性。

公开(公告)号：US20160013300A1

公开(公告)日：2016-01-14

申请号：US14770448

申请日：2013-02-25

Applicant: HITACHI, LTD.

Inventor： Takayuki HASHIMOTO ,  Mutsuhiro MORI

IPC: H01L29/739 ,  H01L29/36 ,  H02M7/537 ,  H01L29/423

CPC classification number: H01L29/7391 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/7393 ,  H01L29/7813 ,  H02M7/537 ,  H03K2017/307

Abstract: A semiconductor device according to the present invention includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type adjacent to the first semiconductor layer and having an impurity concentration lower than the first semiconductor layer; a third semiconductor layer of a second conductivity type adjacent to the second semiconductor layer; a fourth semiconductor layer of the first conductivity type located within the third semiconductor layer; a first electrode coupled to the third semiconductor layer and the fourth semiconductor layer; a second electrode coupled to the first semiconductor layer; and an insulated gate provided over the respective surfaces of the third semiconductor layer and the fourth semiconductor layer, wherein peak value of the impurity concentration of the third semiconductor layer is in the range of 2×1016 cm−3 or more and 5×1018 cm−3 or less.

Abstract translation: 根据本发明的半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层，与第一半导体层相邻，杂质浓度低于第一半导体层; 与第二半导体层相邻的第二导电类型的第三半导体层; 位于第三半导体层内的第一导电类型的第四半导体层; 耦合到所述第三半导体层和所述第四半导体层的第一电极; 耦合到所述第一半导体层的第二电极; 以及设置在所述第三半导体层和所述第四半导体层的各个表面上的绝缘栅极，其中所述第三半导体层的杂质浓度的峰值在2×10 16 cm -3以上且5×10 18 cm的范围内 -3以下。

公开(公告)号：US20160013299A1

公开(公告)日：2016-01-14

申请号：US14770443

申请日：2013-02-25

Applicant: HITACHI, LTD.

Inventor： Takayuki HASHIMOTO ,  Mutsuhiro MORI

IPC: H01L29/739 ,  H01L29/36 ,  H02M7/53 ,  H01L29/423

CPC classification number: H01L29/7391 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/7393 ,  H02M7/53 ,  H03K2017/307

Abstract: A semiconductor device according to the present invention includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type, which is adjacent to the first semiconductor layer and has an impurity concentration lower than the first semiconductor layer; a third semiconductor layer adjacent to the second semiconductor layer; a first electrode electrically coupled to the third semiconductor layer; a second electrode electrically coupled to the first semiconductor layer; and an insulated gate provided over the surface of the third semiconductor layer. Then, an end portion of the insulated gate is located at a position distant from the junction part between the second semiconductor layer and the third semiconductor layer within the surface of the third semiconductor layer.

Abstract translation: 根据本发明的半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层，其与第一半导体层相邻并且具有低于第一半导体层的杂质浓度; 与所述第二半导体层相邻的第三半导体层; 电耦合到所述第三半导体层的第一电极; 电耦合到所述第一半导体层的第二电极; 以及设置在第三半导体层的表面上的绝缘栅极。 然后，绝缘栅极的端部位于远离第三半导体层的表面内的第二半导体层和第三半导体层之间的接合部的位置。

公开(公告)号：US20170141677A1

公开(公告)日：2017-05-18

申请号：US15420393

申请日：2017-01-31

Applicant: Hitachi, Ltd.

Inventor： Takayuki HASHIMOTO ,  Mutsuhiro MORI ,  Masahiro MASUNAGA

IPC: H02M1/088 ,  H01L29/10 ,  H02M7/5387 ,  H01L29/417 ,  H01L29/739 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08

CPC classification number: H02M1/088 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1079 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7394 ,  H01L29/7396 ,  H01L29/7397 ,  H02M1/08 ,  H02M7/003 ,  H02M7/537 ,  H02M7/5387 ,  H02M2001/0054

Abstract: The present invention provides a switching device (100) for power conversion in which a first gate electrode (6), a p-type channel layer (2) having an n-type emitter region (3), a second gate electrode (13), and a p-type floating layer (15) are repeatedly arranged in order on the surface side of an n−type semiconductor substrate (1). An interval a between the two gates (6, 13) that sandwich the p-type channel layer (2) is configured to be smaller than an interval b between the two gates (13, 6) that sandwich the p-type floating layer (15). The first gate electrode (6) and the second gate electrode (13) are both supplied with drive signals having a time difference in drive timing.

公开(公告)号：US20140070379A1

公开(公告)日：2014-03-13

申请号：US13973802

申请日：2013-08-22

Applicant: Hitachi, Ltd.

Inventor： Tetsuya ISHIMARU ,  Mutsuhiro MORI

IPC: H01L29/861

CPC classification number: H01L29/8611 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/872

Abstract: A diode includes: a first semiconductor layer of a first conductive type; a second semiconductor layer of a second conductive type arranged adjoining to the first semiconductor layer; a third semiconductor layer of the first conductive type arranged on a side, opposite to the second semiconductor layer, of the first semiconductor layer, and contains a dopant of the first conductive type at a higher concentration than the first semiconductor layer; a first electrode ohmically connected to the second semiconductor layer; a second electrode ohmically connected to the third semiconductor layer; and a fourth semiconductor layer arranged at a position adjoining to the third semiconductor layer between the first and third semiconductor layers, contains a dopant of a type being the same as a type of the dopant of the first conductive type contained in the third semiconductor layer, and has a carrier lifetime shorter than the third semiconductor layer.

Abstract translation: 二极管包括：第一导电类型的第一半导体层; 与第一半导体层相邻布置的第二导电类型的第二半导体层; 第一导电类型的第三半导体层布置在第一半导体层的与第二半导体层相对的一侧上，并且包含比第一半导体层更高的浓度的第一导电类型的掺杂剂; 欧姆连接到第二半导体层的第一电极; 欧姆连接到第三半导体层的第二电极; 以及布置在与所述第三半导体层之间的所述第三半导体层相邻的位置的位置处的第四半导体层，包含与所述第三半导体层中包含的所述第一导电类型的掺杂剂的类型相同的掺杂剂， 并且具有比第三半导体层短的载流子寿命。

公开(公告)号：US20170373599A1

公开(公告)日：2017-12-28

申请号：US15699274

申请日：2017-09-08

Applicant: HITACHI, LTD.

Inventor： Takayuki HASHIMOTO ,  Mutsuhiro MORI

IPC: H02M3/158 ,  H02M1/32 ,  H03K17/082 ,  H01L29/786 ,  H02M1/00 ,  H03K17/16

CPC classification number: H02M3/158 ,  H01L29/786 ,  H02M1/00 ,  H02M1/32 ,  H02M2001/0009 ,  H03K17/0828 ,  H03K17/168 ,  H03K2217/0036

Abstract: An apparatus is adapted to drive an insulating gate-type semiconductor element by a first control voltage and a second control voltage, that are supplied to a first insulating gate and a second insulating gate, respectively, and includes a first noise filter inputting a signal about current that passes through the insulating gate-type semiconductor element, a first comparator making a comparison between an output signal of the first noise filter and a first reference signal and outputting a first comparison result, a first control voltage output circuit, and a second control voltage output circuit, the second control voltage output circuit being adapted to reduce the second control voltage when it is determined from the first comparison result that overcurrent passes through the insulating gate-type semiconductor element, the first control voltage output circuit being adapted to reduce the first control voltage after the second control voltage is reduced.

公开(公告)号：US20150340965A1

公开(公告)日：2015-11-26

申请号：US14719413

申请日：2015-05-22

Applicant: Hitachi, Ltd.

Inventor： Takashi HIRAO ,  Mutsuhiro MORI

IPC: H02M7/537 ,  H01L27/06

CPC classification number: H02M7/537 ,  H01L27/0629 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/7397 ,  H01L29/8611 ,  H02M7/003 ,  H03K17/16 ,  H03K17/74

Abstract: A semiconductor device is provided that can prevent a current from being concentrated into a specific chip, and can reduce loss as well as noise. The semiconductor device according to the present invention includes: a switching element; a main diode that is connected in parallel to the switching element; and an auxiliary diode that is connected in parallel to the switching element and has a different structure from that of the main diode, wherein in a conductive state a current flowing through the auxiliary diode is smaller than that through the main diode, and in a transition period from the conductive state to a non-conductive state a current flowing through the auxiliary diode is larger than that through the main diode.

Abstract translation: 提供了可以防止电流集中到特定芯片中的半导体器件，并且可以减少损耗以及噪声。 根据本发明的半导体器件包括：开关元件; 与开关元件并联连接的主二极管; 以及与开关元件并联连接并且与主二极管的结构不同的辅助二极管，其中在导通状态下，流过辅助二极管的电流小于通过主二极管的电流，并且在转换中 从导通状态到非导通状态的时间段，流过辅助二极管的电流大于通过主二极管的电流。