公开(公告)号：US20240234359A9

公开(公告)日：2024-07-11

申请号：US18566303

申请日：2022-02-21

Applicant: Hitachi Astemo, Ltd.

Inventor： Osamu IKEDA ,  Naoki SAKURAI ,  Takayuki OSHIMA ,  Takuma HAKUTO

IPC: H01L23/00

CPC classification number: H01L24/29 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/278 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/4846

Abstract: A semiconductor device includes a semiconductor element having an Ni—V electrode and a conductor, the semiconductor element and the conductor being bonded via Sn-based lead-free solder. In the semiconductor device, an Sn—V compound layer and an (Ni, Cu)3Sn4 compound layer adjacent to the Sn—V compound are formed adjacent to an interface between the semiconductor element and the Sn-based lead-free solder. A manufacturing method for a semiconductor device according to the present invention includes: causing the Sn-based lead-free solder and the Ni—V electrode to react with each other to form an Sn—V layer and an (Ni, Cu)3Sn4 compound layer; and following formation of the Sn—V layer, leaving an unreacted layer of the Ni—V electrode, the unreacted layer having not reacted with the Sn-based lead-free solder, intact.

公开(公告)号：US20220108940A1

公开(公告)日：2022-04-07

申请号：US17429464

申请日：2020-01-15

Applicant: Hitachi Astemo, Ltd.

Inventor： Yusuke TAKAGI ,  Ryo TERAYAMA ,  Ko HAMAYA ,  Osamu IKEDA

IPC: H01L23/495

Abstract: A power semiconductor module, which is a semiconductor device, includes a semiconductor element 155 and a lead frame 318 that is disposed to face the semiconductor element 155 and connected to the semiconductor element 155 by a solder material 162. The lead frame 318 has the top surface 331 including a surface facing the semiconductor element 155, and the side surface 334 connected to the peripheral edge portion 333 of the top surface 331 at a predetermined angle with respect to the top surface 331. The top surface of the lead frame 318 includes the solder surface 332 that is in contact with the solder material 162 and the solder resistance surface on which the solder material 162 is less wettable than on the solder surface 332. The solder resistance surface is formed to surround the periphery of the solder surface 332. In this manner, when the semiconductor element and the lead frame are solder-joined in the semiconductor device, the region where the solder wet-spreads is appropriately controlled.

公开(公告)号：US20240136318A1

公开(公告)日：2024-04-25

申请号：US18566303

申请日：2022-02-21

Applicant: Hitachi Astemo, Ltd.

Inventor： Osamu IKEDA ,  Naoki SAKURAI ,  Takayuki OSHIMA ,  Takuma HAKUTO

IPC: H01L23/00

CPC classification number: H01L24/29 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/278 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/4846

Abstract: A semiconductor device includes a semiconductor element having an Ni—V electrode and a conductor, the semiconductor element and the conductor being bonded via Sn-based lead-free solder. In the semiconductor device, an Sn—V compound layer and an (Ni, Cu)3Sn4 compound layer adjacent to the Sn—V compound are formed adjacent to an interface between the semiconductor element and the Sn-based lead-free solder. A manufacturing method for a semiconductor device according to the present invention includes: causing the Sn-based lead-free solder and the Ni—V electrode to react with each other to form an Sn—V layer and an (Ni, Cu)3Sn4 compound layer; and following formation of the Sn—V layer, leaving an unreacted layer of the Ni—V electrode, the unreacted layer having not reacted with the Sn-based lead-free solder, intact.

公开(公告)号：US20230298983A1

公开(公告)日：2023-09-21

申请号：US17928724

申请日：2021-02-26

Applicant: Hitachi Astemo, Ltd.

Inventor： Osamu IKEDA ,  Yusuke TAKAGI ,  Yujiro KANEKO ,  Shota FUNATO

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49582 ,  H01L24/32 ,  H01L24/33 ,  H01L24/29 ,  H01L21/4821 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/29139 ,  H01L2224/83801 ,  H01L2224/83455 ,  H01L2224/83447

Abstract: A semiconductor device includes: a semiconductor element; and a first conductor and a second conductor respectively joined to a first surface and a second surface of the semiconductor element via Sn-based solder, in which a Ni-based plated layer is formed on surfaces of the first conductor and the second conductor that oppose the Sn-based solder and on the first surface and the second surface of the semiconductor element, and an interface reaction inhibition layer made of (Cu, Ni)6Sn5 and having a layer thickness of 1.2 to 4.0 μm is formed at an interface between the Ni-based plated layer and the Sn-based solder.

公开(公告)号：US20220295642A1

公开(公告)日：2022-09-15

申请号：US17632931

申请日：2020-05-11

Applicant: Hitachi Astemo, Ltd.

Inventor： Osamu IKEDA ,  Shiro YAMASHITA

IPC: H05K3/34 ,  H01L23/12 ,  B23K35/26

Abstract: An electronic control device includes: a circuit board; an electronic component; and a bonding portion bonding the circuit board and the electronic component to each other. The bonding portion contains Sn as a main component, Bi and Sb in a total content ratio of 3 wt % or more, and Ag in a content of 3 to 3.9 wt %, with no In.