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1.发明授权Assessing metal stack integrity in sophisticated semiconductor devices by mechanically stressing die contacts 有权通过机械应力模具接触来评估复杂半导体器件中的金属堆叠完整性公开(公告)号：US08479578B2
公开(公告)日：2013-07-09
申请号：US12939471
申请日：2010-11-04
CPC分类号： H01L22/12 , H01L24/13 , H01L2224/131 , H01L2224/13147 , H01L2924/00013 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/01327 , H01L2924/10253 , H01L2924/1306 , H01L2924/14 , H01L2924/35 , H01L2924/01014 , H01L2924/00014 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： The metallization system of complex semiconductor devices may be evaluated in terms of mechanical integrity on the basis of a measurement system and measurement procedures in which individual contact elements, such as metal pillars or solder bumps, are mechanically stimulated, while the response of the metallization system, for instance in the form of directly measured forces, is determined in order to quantitatively evaluate mechanical status of the metallization system. In this manner, the complex material systems and the mutual interactions thereof may be efficiently assessed.
摘要翻译： 复合半导体器件的金属化系统可以基于测量系统和测量程序在机械完整性方面进行评估，其中单个接触元件例如金属柱或焊料凸块被机械刺激，同时金属化系统的响应 确定例如以直接测量的力的形式，以定量地评估金属化系统的机械状态。 以这种方式，可以有效地评估复杂材料体系及其相互作用。
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2.发明申请ASSESSING METAL STACK INTEGRITY IN SOPHISTICATED SEMICONDUCTOR DEVICES BY MECHANICALLY STRESSING DIE CONTACTS 有权通过机械压力连接器来评估机械半导体器件中的金属堆积整合公开(公告)号：US20110209548A1
公开(公告)日：2011-09-01
申请号：US12939471
申请日：2010-11-04
CPC分类号： H01L22/12 , H01L24/13 , H01L2224/131 , H01L2224/13147 , H01L2924/00013 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/01327 , H01L2924/10253 , H01L2924/1306 , H01L2924/14 , H01L2924/35 , H01L2924/01014 , H01L2924/00014 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： The metallization system of complex semiconductor devices may be evaluated in terms of mechanical integrity on the basis of a measurement system and measurement procedures in which individual contact elements, such as metal pillars or solder bumps, are mechanically stimulated, while the response of the metallization system, for instance in the form of directly measured forces, is determined in order to quantitatively evaluate mechanical status of the metallization system. In this manner, the complex material systems and the mutual interactions thereof may be efficiently assessed.
摘要翻译： 复合半导体器件的金属化系统可以基于测量系统和测量程序在机械完整性方面进行评估，其中单个接触元件例如金属柱或焊料凸块被机械刺激，同时金属化系统的响应 确定例如以直接测量的力的形式，以定量地评估金属化系统的机械状态。 以这种方式，可以有效地评估复杂材料体系及其相互作用。
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3.发明授权Assessing thermal mechanical characteristics of complex semiconductor devices by integrated heating systems 有权通过综合加热系统评估复杂半导体器件的热机械特性公开(公告)号：US08920027B2
公开(公告)日：2014-12-30
申请号：US13187203
申请日：2011-07-20
CPC分类号： H01L22/34 , H01L22/12 , H01L23/345 , H01L24/16 , H01L2224/131 , H01L2924/01019 , H01L2924/1306 , H01L2924/14 , H01L2924/014 , H01L2924/00
摘要： In a semiconductor device or test structure, appropriate heating elements, for instance in the form of resistive structures, are implemented so as to obtain superior area coverage, thereby enabling a precise evaluation of the thermal conditions within a complex semiconductor device. In particular, the device internal heating elements may allow the evaluation of hot spots and the response of a complex metallization system to specific temperature profiles, in particular at critical areas, such as edge regions in which mechanical stress forces are typically highest in contact regimes in which the package substrate and the metallization system are directly connected.
摘要翻译： 在半导体器件或测试结构中，实施适当的加热元件，例如以电阻结构的形式，以获得优异的面积覆盖，从而能够对复杂半导体器件内的热条件进行精确评估。 特别地，设备内部加热元件可以允许评估热点和复杂金属化系统对特定温度分布的响应，特别是在关键区域，例如边界区域，其中机械应力通常在接触方式中最高 封装衬底和金属化系统直接连接。
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4.发明申请Applying Thermal Mechanical Characteristics of Complex Semiconductor Devices by Integrated Heating Systems 有权通过综合加热系统应用复杂半导体器件的热机械特性公开(公告)号：US20120051392A1
公开(公告)日：2012-03-01
申请号：US13187203
申请日：2011-07-20
CPC分类号： H01L22/34 , H01L22/12 , H01L23/345 , H01L24/16 , H01L2224/131 , H01L2924/01019 , H01L2924/1306 , H01L2924/14 , H01L2924/014 , H01L2924/00
摘要： In a semiconductor device or test structure, appropriate heating elements, for instance in the form of resistive structures, are implemented so as to obtain superior area coverage, thereby enabling a precise evaluation of the thermal conditions within a complex semiconductor device. In particular, the device internal heating elements may allow the evaluation of hot spots and the response of a complex metallization system to specific temperature profiles, in particular at critical areas, such as edge regions in which mechanical stress forces are typically highest in contact regimes in which the package substrate and the metallization system are directly connected.
摘要翻译： 在半导体器件或测试结构中，实施适当的加热元件，例如以电阻结构的形式，以获得优异的面积覆盖，从而能够对复杂半导体器件内的热条件进行精确评估。 特别地，设备内部加热元件可以允许评估热点和复杂金属化系统对特定温度分布的响应，特别是在关键区域，例如边界区域，其中机械应力通常在接触方式中最高 封装衬底和金属化系统直接连接。
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5.发明申请METHOD AND TEST STRUCTURE FOR MONITORING CMP PROCESSES IN METALLIZATION LAYERS OF SEMICONDUCTOR DEVICES 有权用于监测半导体器件金属化层中CMP工艺的方法和测试结构公开(公告)号：US20090140246A1
公开(公告)日：2009-06-04
申请号：US12165725
申请日：2008-07-01
申请人： Michael Grillberger , Matthias Lehr
发明人： Michael Grillberger , Matthias Lehr
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： By forming a large metal pad and removing any excess material thereof, a pronounced recessed surface topography may be obtained, which may also affect the further formation of a metallization layer of a semiconductor device, thereby increasing the probability of maintaining metal residues above the recessed surface topography. Consequently, by providing test metal lines in the area of the recessed surface topography, the performance of a respective CMP process may be estimated with increased efficiency.
摘要翻译： 通过形成大的金属焊盘并除去其中多余的材料，可以获得显着的凹陷表面形貌，这也可能影响半导体器件的金属化层的进一步形成，从而增加在凹陷表面上保持金属残余物的可能性 地形。 因此，通过在凹形表面形貌的区域中提供测试金属线，可以以更高的效率来估计各个CMP工艺的性能。
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6.发明授权Method and test structure for monitoring CMP processes in metallization layers of semiconductor devices 有权用于监测半导体器件的金属化层中的CMP工艺的方法和测试结构公开(公告)号：US07829357B2
公开(公告)日：2010-11-09
申请号：US12165725
申请日：2008-07-01
申请人： Michael Grillberger , Matthias Lehr
发明人： Michael Grillberger , Matthias Lehr
IPC分类号： H01L21/00
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： By forming a large metal pad and removing any excess material thereof, a pronounced recessed surface topography may be obtained, which may also affect the further formation of a metallization layer of a semiconductor device, thereby increasing the probability of maintaining metal residues above the recessed surface topography. Consequently, by providing test metal lines in the area of the recessed surface topography, the performance of a respective CMP process may be estimated with increased efficiency.
摘要翻译： 通过形成大的金属焊盘并除去其中多余的材料，可以获得显着的凹陷表面形貌，这也可能影响半导体器件的金属化层的进一步形成，从而增加在凹陷表面上保持金属残余物的可能性 地形。 因此，通过在凹形表面形貌的区域中提供测试金属线，可以以更高的效率来估计各个CMP工艺的性能。
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7.发明申请SEMICONDUCTOR DEVICE COMPRISING A CHIP INTERNAL ELECTRICAL TEST STRUCTURE ALLOWING ELECTRICAL MEASUREMENTS DURING THE FABRICATION PROCESS 审中-公开在制造过程中包含芯片内部电气测试结构允许电气测量的半导体器件公开(公告)号：US20100252828A1
公开(公告)日：2010-10-07
申请号：US12417749
申请日：2009-04-03
申请人： Michael Grillberger , Matthias Lehr
发明人： Michael Grillberger , Matthias Lehr
IPC分类号： H01L23/00 , H01L21/66 , H01L21/768
CPC分类号： H01L23/585 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A test structure or a circuit element acting temporarily as a test structure may be provided within the die region of sophisticated semiconductor devices, while probe pads may be located in the frame in order to not unduly consume valuable die area. The electrical connection between the test structure and the probe pads may be established by a conductive path including a buried portion, which extends from the die region into the frame below a die seal, thereby maintaining the electrical and mechanical characteristics of the die seal. Hence, enhanced availability of electrical measurement data and superior authenticity of the data may be accomplished, wherein the measurement data may be obtained during the production process.
摘要翻译： 作为测试结构临时作用的测试结构或电路元件可以设置在复杂半导体器件的管芯区域内，而探针焊盘可以位于框架中，以便不会不当地消耗有价值的管芯区域。 测试结构和探针焊盘之间的电连接可以通过包括埋入部分的导电路径建立，所述掩埋部分从模具区域延伸到模具密封件下方的框架中，从而保持模具密封件的电气和机械特性。 因此，可以实现电测量数据的增强的可用性和数据的真实性，其中可以在生产过程期间获得测量数据。
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8.发明申请SEMICONDUCTOR DEVICE INCLUDING STRESS RELAXATION GAPS FOR ENHANCING CHIP PACKAGE INTERACTION STABILITY 有权半导体器件，包括用于增强芯片封装相互作用稳定性的应力松弛GAPS公开(公告)号：US20100052147A1
公开(公告)日：2010-03-04
申请号：US12507348
申请日：2009-07-22
申请人： Michael Grillberger , Matthias Lehr
发明人： Michael Grillberger , Matthias Lehr
IPC分类号： H01L23/52 , H01L23/498 , H01L21/50
CPC分类号： H01L23/5283 , H01L23/3677 , H01L23/562 , H01L2224/05001 , H01L2224/05022 , H01L2224/051 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2924/12044 , H01L2924/1433 , H01L2924/00014
摘要： By dividing a single chip area into individual sub-areas, a thermally induced stress in each of the sub-areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip may be used compared to conventional strategies.
摘要翻译： 通过将单个芯片区域划分成单个子区域，在复杂集成电路的操作期间，可以减少每个子区域中的热诱导应力，从而增强包括低k电介质材料或ULK的复杂金属化系统的整体可靠性 材料。 因此，与常规策略相比，可以使用大量堆叠的金属化层与半导体芯片的增加的横向尺寸的组合。
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9.发明授权Reduction of mechanical stress in metal stacks of sophisticated semiconductor devices during die-substrate soldering by an enhanced cool down regime 有权通过增强的冷却方式在模具衬底焊接期间减少复杂半导体器件的金属堆叠中的机械应力公开(公告)号：US08501545B2
公开(公告)日：2013-08-06
申请号：US12963134
申请日：2010-12-08
CPC分类号： H01L24/81 , H01L24/13 , H01L24/16 , H01L24/75 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/75251 , H01L2224/75253 , H01L2224/81193 , H01L2224/81385 , H01L2224/81815 , H01L2224/81948 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/01047 , H01L2924/0105 , H01L2924/01068 , H01L2924/01075 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/14 , H01L2924/351 , H01L2924/00
摘要： In a reflow process for connecting a semiconductor die and a package substrate, the temperature gradient and thus the thermally induced mechanical forces in a sensitive metallization system of the semiconductor die may be reduced during the cooling phase. To this end, one or more heating intervals may be introduced into the cooling phase, thereby efficiently reducing the temperature difference. In other cases, the central region may additionally be cooled by providing appropriate locally restricted mechanisms, such as a locally restricted gas flow and the like. Consequently, desired short overall process times may be obtain without contributing to increased yield losses when processing sophisticated metallization systems on the basis of a lead-free contact regime.
摘要翻译： 在用于连接半导体管芯和封装衬底的回流工艺中，可以在冷却阶段期间降低半导体管芯的敏感金属化系统中的温度梯度和热诱导的机械力。 为此，可以将一个或多个加热间隔引入冷却阶段，从而有效地降低温差。 在其他情况下，中心区域可以另外通过提供适当的局部限制的机构（例如局部限制的气流等）而被冷却。 因此，可以获得期望的短整体工艺时间，而不会在基于无铅接触方式处理复杂的金属化系统时增加产量损失。
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10.发明申请Reduction of Mechanical Stress in Metal Stacks of Sophisticated Semiconductor Devices During Die-Substrate Soldering by an Enhanced Cool Down Regime 有权通过增强的冷却方式在模底板焊接期间减少精密半导体器件的金属堆叠中的机械应力公开(公告)号：US20110244632A1
公开(公告)日：2011-10-06
申请号：US12963134
申请日：2010-12-08
CPC分类号： H01L24/81 , H01L24/13 , H01L24/16 , H01L24/75 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/75251 , H01L2224/75253 , H01L2224/81193 , H01L2224/81385 , H01L2224/81815 , H01L2224/81948 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/01047 , H01L2924/0105 , H01L2924/01068 , H01L2924/01075 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/14 , H01L2924/351 , H01L2924/00
摘要： In a reflow process for connecting a semiconductor die and a package substrate, the temperature gradient and thus the thermally induced mechanical forces in a sensitive metallization system of the semiconductor die may be reduced during the cooling phase. To this end, one or more heating intervals may be introduced into the cooling phase, thereby efficiently reducing the temperature difference. In other cases, the central region may additionally be cooled by providing appropriate locally restricted mechanisms, such as a locally restricted gas flow and the like. Consequently, desired short overall process times may be obtain without contributing to increased yield losses when processing sophisticated metallization systems on the basis of a lead-free contact regime.
摘要翻译： 在用于连接半导体管芯和封装衬底的回流工艺中，可以在冷却阶段期间降低半导体管芯的敏感金属化系统中的温度梯度和热诱导的机械力。 为此，可以将一个或多个加热间隔引入冷却阶段，从而有效地降低温差。 在其他情况下，中心区域可以另外通过提供适当的局部限制的机构（例如局部限制的气流等）而被冷却。 因此，可以获得期望的短整体工艺时间，而不会在基于无铅接触方式处理复杂的金属化系统时增加产量损失。
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