DISPLAY SUBSTRATE AND A METHOD OF MANUFACTURING THE DISPLAY SUBSTRATE
    4.
    发明申请
    DISPLAY SUBSTRATE AND A METHOD OF MANUFACTURING THE DISPLAY SUBSTRATE 审中-公开
    显示基板和制造显示基板的方法

    公开(公告)号:US20090184319A1

    公开(公告)日:2009-07-23

    申请号:US12328487

    申请日:2008-12-04

    IPC分类号: H01L29/04 H01L21/336

    摘要: A method of manufacturing a display substrate is described. In the method, a gate line and a gate electrode are formed on a base substrate. A source metal layer is formed on the base substrate having the gate line and the gate electrode. A data line, a source electrode and a drain electrode are formed by etching the source metal layer by using an etching gas. An additive gas is provided to the base substrate having the drain electrode so that the additive gas reacts with an etching component of the etching gas to remove a by-product formed at an exposed portion of the data line, the source electrode and drain electrode. Thus, corrosion of the fine pattern due to an etching gas may be prevented and/or reduced.

    摘要翻译: 对制造显示基板的方法进行说明。 在该方法中,在基底基板上形成栅极线和栅电极。 在具有栅极线和栅电极的基底基板上形成源极金属层。 通过使用蚀刻气体蚀刻源极金属层来形成数据线,源电极和漏电极。 向具有漏电极的基底基板提供添加气体,使得添加气体与蚀刻气体的蚀刻部件反应,以除去在数据线,源电极和漏电极的暴露部分形成的副产物。 因此,可以防止和/或减少由蚀刻气体引起的精细图案的腐蚀。

    DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    显示基板及其制造方法

    公开(公告)号:US20070164330A1

    公开(公告)日:2007-07-19

    申请号:US11566886

    申请日:2006-12-05

    IPC分类号: H01L31/113

    摘要: A display substrate includes a base substrate, a first metal pattern, a gate insulating layer, a second metal pattern, a channel layer and a pixel electrode. The first metal pattern is formed on the base substrate, and includes a gate line and a gate electrode of a switching element. The gate insulating layer is formed on the base substrate including the first metal pattern. The second metal pattern is formed on the gate insulating layer, and includes a source electrode, a drain electrode and a source line. The channel layer is formed under the second metal pattern, and is patterned to have substantially the same side surface as a side surface of the second metal pattern. The pixel electrode is electrically connected to the drain electrode. Therefore, an afterimage on a display panel, thus improving display quality.

    摘要翻译: 显示基板包括基底基板,第一金属图案,栅极绝缘层,第二金属图案,沟道层和像素电极。 第一金属图案形成在基底基板上,并且包括开关元件的栅极线和栅电极。 栅极绝缘层形成在包括第一金属图案的基底基板上。 第二金属图案形成在栅极绝缘层上,并且包括源电极,漏电极和源极线。 沟道层形成在第二金属图案之下,并且被图案化以具有与第二金属图案的侧表面基本相同的侧表面。 像素电极电连接到漏电极。 因此,在显示面板上留下余像,从而提高显示质量。

    Signal line for display device and thin film transistor array panel including the signal line
    7.
    发明授权
    Signal line for display device and thin film transistor array panel including the signal line 有权
    信号线用于显示器件和薄膜晶体管阵列面板,包括信号线

    公开(公告)号:US07462895B2

    公开(公告)日:2008-12-09

    申请号:US11296603

    申请日:2005-12-06

    IPC分类号: H01L29/10

    摘要: A thin film transistor (TFT) array panel with signal lines that have low resistivity is presented. The TFT array panel includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating layer formed on the gate line, a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode facing the source electrode with a gap, and a pixel electrode connected to the drain electrode. In one embodiment, at least one of the gate line, the data line, and the drain electrode includes a first conductive layer made of a Mo-containing conductor, a second conductive layer made of a Cu-containing conductor, and a third conductive layer made of a MoN-containing conductor.

    摘要翻译: 提出了具有低电阻率的信号线的薄膜晶体管(TFT)阵列面板。 TFT阵列面板包括绝缘基板,形成在绝缘基板上的栅极线,形成在栅极线上的栅极绝缘层,漏极电极和形成在栅极绝缘层上的源电极的数据线, 具有间隙的源电极和连接到漏电极的像素电极。 在一个实施例中,栅极线,数据线和漏电极中的至少一个包括由含Mo导体制成的第一导电层,由含Cu导体制成的第二导电层和第三导电层 由含MoN的导体制成。

    SIGNAL LINE FOR DISPLAY DEVICE AND THIN FILM TRANSISTOR ARRAY PANEL INCLUDING THE SIGNAL LINE
    9.
    发明申请
    SIGNAL LINE FOR DISPLAY DEVICE AND THIN FILM TRANSISTOR ARRAY PANEL INCLUDING THE SIGNAL LINE 有权
    用于显示器件的信号线和包括信号线的薄膜晶体管阵列

    公开(公告)号:US20090130789A1

    公开(公告)日:2009-05-21

    申请号:US12269603

    申请日:2008-11-12

    IPC分类号: H01L33/00

    摘要: A thin film transistor (TFT) array panel with signal lines that have low resistivity is presented. The TFT array panel includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating layer formed on the gate line, a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode facing the source electrode with a gap, and a pixel electrode connected to the drain electrode. In one embodiment, at least one of the gate line, the data line, and the drain electrode includes a first conductive layer made of a Mo-containing conductor, a second conductive layer made of a Cu-containing conductor, and a third conductive layer made of a MoN-containing conductor.

    摘要翻译: 提出了具有低电阻率的信号线的薄膜晶体管(TFT)阵列面板。 TFT阵列面板包括绝缘基板,形成在绝缘基板上的栅极线,形成在栅极线上的栅极绝缘层,漏极电极和形成在栅极绝缘层上的源电极的数据线, 具有间隙的源电极和连接到漏电极的像素电极。 在一个实施例中,栅极线,数据线和漏电极中的至少一个包括由含Mo导体制成的第一导电层,由含Cu导体制成的第二导电层和第三导电层 由含MoN的导体制成。

    THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, DISPLAY APPARATUS HAVING THE SAME AND METHOD OF MANUFACTURING THE DISPLAY APPARATUS
    10.
    发明申请
    THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, DISPLAY APPARATUS HAVING THE SAME AND METHOD OF MANUFACTURING THE DISPLAY APPARATUS 失效
    薄膜晶体管,其制造方法,具有该方法的显示装置和制造显示装置的方法

    公开(公告)号:US20090017574A1

    公开(公告)日:2009-01-15

    申请号:US12146763

    申请日:2008-06-26

    IPC分类号: H01L21/336 H01L33/00

    摘要: A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.

    摘要翻译: 薄膜晶体管包括衬底上的栅电极,衬底上的栅极绝缘层,沟道图案,源电极和漏电极。 沟道图案包括形成在栅电极上并覆盖栅电极的半导体图案以及形成在半导体图案上并彼此间隔开的第一和第二导电粘合剂图案。 源电极包括顺序地形成在第一导电粘合剂图案上的第一阻挡图案,源图案和第一封盖图案。 漏电极包括顺序地形成在第二导电粘合剂图案上的第二阻挡图案,漏极图案和第二封盖图案。 第一和第二导电粘合剂图案的蚀刻部分具有基本垂直的轮廓,以防止源极和漏极的暴露,从而改善薄膜晶体管的特性。