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公开(公告)号：US20090237996A1
公开(公告)日：2009-09-24
申请号：US12052300
申请日：2008-03-20
CPC分类号： G11C14/0018 , G11C16/0466 , H01L27/105 , H01L27/1052 , H01L27/10826 , H01L27/10876 , H01L27/10894 , H01L27/11568 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.
摘要翻译： 提供一种存储器阵列，其包括具有共享晶体管的源极，漏极和沟道的两个有源栅极的晶体管。 有源栅极中的一个可以耦合到诸如DRAM单元的存储器单元的易失性存储器部分，并且另一有源栅极可以耦合到非易失性存储器部分，例如电荷存储节点，例如 SONOS细胞。 提供了操作存储器阵列的方法，其包括将数据从易失性存储器部分传送到非易失性存储器部分，将数据从非易失性存储器部分传送到易失性存储器部分，以及擦除非易失性存储器部分 行的存储单元。
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公开(公告)号：US20110127596A1
公开(公告)日：2011-06-02
申请号：US13026052
申请日：2011-02-11
IPC分类号： H01L27/108 , H01L29/792 , H01L27/088
CPC分类号： G11C14/0018 , G11C16/0466 , H01L27/105 , H01L27/1052 , H01L27/10826 , H01L27/10876 , H01L27/10894 , H01L27/11568 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.
摘要翻译： 提供一种存储器阵列，其包括具有共享晶体管的源极，漏极和沟道的两个有源栅极的晶体管。 有源栅极中的一个可以耦合到诸如DRAM单元的存储器单元的易失性存储器部分，并且另一有源栅极可以耦合到非易失性存储器部分，例如电荷存储节点，例如 SONOS细胞。 提供了操作存储器阵列的方法，其包括将数据从易失性存储器部分传送到非易失性存储器部分，将数据从非易失性存储器部分传送到易失性存储器部分，以及擦除非易失性存储器部分的非易失性存储器部分 行的存储单元。
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公开(公告)号：US08149619B2
公开(公告)日：2012-04-03
申请号：US13026052
申请日：2011-02-11
IPC分类号： G11C14/00
CPC分类号： G11C14/0018 , G11C16/0466 , H01L27/105 , H01L27/1052 , H01L27/10826 , H01L27/10876 , H01L27/10894 , H01L27/11568 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.
摘要翻译： 提供一种存储器阵列，其包括具有共享晶体管的源极，漏极和沟道的两个有源栅极的晶体管。 有源栅极中的一个可以耦合到诸如DRAM单元的存储器单元的易失性存储器部分，并且另一有源栅极可以耦合到非易失性存储器部分，例如电荷存储节点，例如 SONOS细胞。 提供了操作存储器阵列的方法，其包括将数据从易失性存储器部分传送到非易失性存储器部分，将数据从非易失性存储器部分传送到易失性存储器部分，以及擦除非易失性存储器部分的非易失性存储器部分 行的存储单元。
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公开(公告)号：US07898857B2
公开(公告)日：2011-03-01
申请号：US12052300
申请日：2008-03-20
IPC分类号： G11C16/04
CPC分类号： G11C14/0018 , G11C16/0466 , H01L27/105 , H01L27/1052 , H01L27/10826 , H01L27/10876 , H01L27/10894 , H01L27/11568 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.
摘要翻译： 提供一种存储器阵列，其包括具有共享晶体管的源极，漏极和沟道的两个有源栅极的晶体管。 有源栅极中的一个可以耦合到诸如DRAM单元的存储器单元的易失性存储器部分，并且另一有源栅极可以耦合到非易失性存储器部分，例如电荷存储节点，例如 SONOS细胞。 提供了操作存储器阵列的方法，其包括将数据从易失性存储器部分传送到非易失性存储器部分，将数据从非易失性存储器部分传送到易失性存储器部分，以及擦除非易失性存储器部分的非易失性存储器部分 行的存储单元。
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公开(公告)号：US07480202B2
公开(公告)日：2009-01-20
申请号：US12072125
申请日：2008-02-22
申请人： Huy Vo , Charles Ingalls
发明人： Huy Vo , Charles Ingalls
IPC分类号： G11C8/00
CPC分类号： G11C7/1069 , G11C7/1012 , G11C7/1039 , G11C7/1042 , G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1096 , G11C11/4096 , G11C2207/002
摘要： A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline.
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公开(公告)号：US20060268640A1
公开(公告)日：2006-11-30
申请号：US11501144
申请日：2006-08-07
申请人： Sei Yoon , Charles Ingalls , David Pinney , Howard Kirsch
发明人： Sei Yoon , Charles Ingalls , David Pinney , Howard Kirsch
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/04 , G11C7/065 , G11C7/12 , G11C7/14 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.
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公开(公告)号：US20070299092A1
公开(公告)日：2007-12-27
申请号：US11569306
申请日：2005-05-11
申请人： Middleton Floyd Jr , Thomas Nittoli , Allan Wissner , Russell Dushin , Ramaswamy Nilakantan , Charles Ingalls , Heidi Fraser , Bernard Johnson
发明人： Middleton Floyd Jr , Thomas Nittoli , Allan Wissner , Russell Dushin , Ramaswamy Nilakantan , Charles Ingalls , Heidi Fraser , Bernard Johnson
IPC分类号： C07D239/72 , A61K31/517 , A61P19/02 , A61P27/00 , C12N9/99 , A61P3/00 , A61P35/00 , A61P9/00
CPC分类号： C07D239/94 , C07D215/42 , C07D215/54 , C07D401/12 , C07D403/12 , C07D405/12 , C07D409/12 , C07D413/12 , C07D487/08
摘要： The present invention provides for compounds with the general formula: A compound of formula (1) having the structure (1) wherein Z is a radical selected from the group (a), (b), or (c) as well as methods and compositions containing these compounds useful for treatment of diseases that are characterized, at least in part, by excessive, abnormal, or inappropriate angiogenesis. These disease states, include but are not limited to, cancer, diabetic retinopathy, macular degeneration and rheumatoid arthritis. These compounds inhibit angiogenesis by inhibiting a tyrosine kinase receptor enzyme, specifically KDR, and binding to the KDR in an irreversible manner.
摘要翻译： 本发明提供具有以下通式的化合物：具有结构（1）的式（1）化合物，其中Z是选自（a），（b）或（c）的基团，以及方法和 含有这些化合物的组合物可用于治疗至少部分由过度，异常或不合适的血管生成表征的疾病。 这些疾病状态包括但不限于癌症，糖尿病性视网膜病变，黄斑变性和类风湿性关节炎。 这些化合物通过抑制酪氨酸激酶受体酶，特别是KDR，并以不可逆的方式结合KDR来抑制血管生成。
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公开(公告)号：US20060044921A1
公开(公告)日：2006-03-02
申请号：US10928034
申请日：2004-08-27
申请人： Tae Kim , Charles Ingalls , Howard Kirsch , Jeremy Gum
发明人： Tae Kim , Charles Ingalls , Howard Kirsch , Jeremy Gum
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak transistor to ground and a strong transistor to ground. By disabling the wordline driver on the wordlines directly adjacent to the active wordlines, a path is provided to drive the coupling noise from the active wordline to ground through the strong transistor.
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公开(公告)号：US07616504B2
公开(公告)日：2009-11-10
申请号：US12332458
申请日：2008-12-11
申请人： Huy Vo , Charles Ingalls
发明人： Huy Vo , Charles Ingalls
IPC分类号： G11C7/10
CPC分类号： G11C7/1069 , G11C7/1012 , G11C7/1039 , G11C7/1042 , G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1096 , G11C11/4096 , G11C2207/002
摘要： A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline.
摘要翻译： 一种存储器件，包括具有多个存储器单元的存储器阵列和用于将数据读出并将数据写入存储器阵列的多个外围器件，所述外围器件包括连接到第一输入/输出线的第一写入驱动器， 所述第一输入/输出线与连接到所述多个存储器单元中的某些的数字线相关联，连接到所述第一输入/输出线的第一读取放大器，响应于第一列选择信号的第一输入/输出装置， 与数字线的第一输入/输出线，连接到第二输入/输出线的第二写入驱动器，与数字线相关联的第二输入/输出线，连接到第二输入/输出线的第二读取放大器， 输入/输出装置响应于用于将第二输入/输出线连接到数字线的第二列选择信号。
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公开(公告)号：US07352649B2
公开(公告)日：2008-04-01
申请号：US11186525
申请日：2005-07-21
申请人： Huy Vo , Charles Ingalls
发明人： Huy Vo , Charles Ingalls
IPC分类号： G11C8/00
CPC分类号： G11C7/1069 , G11C7/1012 , G11C7/1039 , G11C7/1042 , G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1096 , G11C11/4096 , G11C2207/002
摘要： A memory device including a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline.
摘要翻译： 一种存储器件，包括具有多个存储单元的存储器阵列和用于将数据读出并将数据写入存储器阵列的多个外围设备，所述外围设备包括连接到第一输入/输出线的第一写入驱动器， 所述第一输入/输出线与连接到所述多个存储器单元中的某些的数字线相关联，连接到所述第一输入/输出线的第一读取放大器，响应于第一列选择信号的第一输入/输出装置， 与数字线的第一输入/输出线，连接到第二输入/输出线的第二写入驱动器，与数字线相关联的第二输入/输出线，连接到第二输入/输出线的第二读取放大器， 输入/输出装置响应于用于将第二输入/输出线连接到数字线的第二列选择信号。
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