公开(公告)号：US5523707A

公开(公告)日：1996-06-04

申请号：US497360

申请日：1995-06-30

申请人： Howard L. Levy ,  Eric B. Schorn

发明人： Howard L. Levy ,  Eric B. Schorn

IPC分类号： H03K19/21 ,  G06F7/50

CPC分类号： H03K19/215

摘要： A static XOR gate is provided with circuit speeds necessary to meet the increasing demand of higher computer clock frequencies. The XOR of the present invention takes up less area and consumes less power than prior art XOR circuits. Furthermore, time XOR gate of the present invention is fully static and imposes less constraints on the circuit designer, e.g. no reset logic, input synchronization, or the like. The circuit utilizes only NMOS transistors in the functional logic portion with two output inverters. The circuit elements are symmetrical and have identical input loading, output drive and propagation paths. The XOR of the present invention allows multiple gates to be connected in stages as a "tree" configuration by providing a "push-pull" XOR/EQV (equivalent, i.e. time complement of the XOR output or XNOR) function which is buffered by output inverters to "push" the output to a next stage. Additional transistors are provided to help "pull" internal nodes to the operating voltage but are not logically functional transistors. Further, input connections to the logical transistors are such as to eliminate unnecessary delay between like stages, when configured as a "tree".

摘要翻译： 静态异或门具有满足更高计算机时钟频率日益增长的需求所需的电路速度。 与现有技术的异或电路相比，本发明的XOR占用较少的面积并且消耗更少的功率。 此外，本发明的时间异或门是完全静态的，并且对电路设计者（例如， 无复位逻辑，输入同步等。 该电路仅在功能逻辑部分中使用两个输出反相器的NMOS晶体管。 电路元件是对称的，具有相同的输入负载，输出驱动和传播路径。 本发明的XOR允许多个门通过提供“推挽”XOR / EQV（等效的，即XOR输出或XNOR的时间补码）作为“树”配置分级连接，该功能由输出缓冲 逆变器将输出“推”到下一个阶段。 提供额外的晶体管以帮助将内部节点“拉”到工作电压，但不是逻辑功能的晶体管。 此外，当配置为“树”时，到逻辑晶体管的输入连接是消除类似级之间的不必要的延迟。

公开(公告)号：US07164612B1

公开(公告)日：2007-01-16

申请号：US10683636

申请日：2003-10-10

申请人： Nadeem N. Eleyan ,  Howard L. Levy ,  Jeffrey Y. Su

发明人： Nadeem N. Eleyan ,  Howard L. Levy ,  Jeffrey Y. Su

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2029/5004

摘要： Post-manufacture compensation for a sensing offset can be provided, at least in part, by selectively exposing one of a pair of cross-coupled transistors in a sense amplifier to a bias voltage selected to cause a compensating shift in a characteristic of the exposed transistor. In designs susceptible to post-manufacture data dependent creep in a device characteristic, such exposure may be advantageously provided in situ by causing the sense amplifier to sense values purposefully skewed toward a predominate value selected to cause the compensating shift. In some realizations, an on-chip test block is employed to identify and characterize sensing mismatch. Typically, the techniques described herein may be employed to address sensing offsets that have developed post-manufacture due to a data-dependent effect. However, in some realizations, the techniques described herein may be used to address a sensing offset arising at least in part from other or additional sources.

摘要翻译： 可以至少部分地通过将感测放大器中的一对交叉耦合晶体管中的一个选择性地暴露于所选择的偏置电压以提供暴露的晶体管的特性的补偿偏移来提供用于感测偏移的制造后补偿 。 在易受设备特性的后制造数据依赖性蠕变的设计中，可以有利地通过使读出放大器感测到有选择地偏向所选择的主要值以引起补偿偏移的位置来提供这种曝光。 在一些实现中，使用片上测试块来识别和表征感测不匹配。 通常，本文描述的技术可以用于解决由于数据相关效应而在制造后开发的感测偏移。 然而，在一些实现中，本文描述的技术可以用于解决至少部分地从其他源或附加源产生的感测偏移。

公开(公告)号：US06574160B1

公开(公告)日：2003-06-03

申请号：US10074396

申请日：2002-02-11

申请人： Nadeem N. Eleyan ,  Howard L. Levy ,  Jeffrey Y. Su

发明人： Nadeem N. Eleyan ,  Howard L. Levy ,  Jeffrey Y. Su

IPC分类号： G11C702

CPC分类号： G11C7/04 ,  G11C7/065 ,  G11C2207/065

摘要： According to one embodiment, a memory is disclosed. The memory includes a differential sense amplifier that receives a data input and a complementary data input; and a switching mechanism, coupled to the amplifier, that switches the data input and the complementary data input to minimize a negative bias temperature instability (NBTI) effect on the amplifier.

摘要翻译： 根据一个实施例，公开了一种存储器。 存储器包括接收数据输入和补充数据输入的差分读出放大器; 以及耦合到放大器的切换机构，其切换数据输入和互补数据输入以最小化对放大器的负偏压温度不稳定性（NBTI）效应。

公开(公告)号：US20100274961A1

公开(公告)日：2010-10-28

申请号：US12428457

申请日：2009-04-22

申请人： Robert T. Golla ,  Jama I. Barreh ,  Howard L. Levy

发明人： Robert T. Golla ,  Jama I. Barreh ,  Howard L. Levy

IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F12/00

CPC分类号： G06F9/3851 ,  G06F9/30112 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3877

摘要： Techniques and systems are described herein to maintain a mapping of logical to physical registers—for example, in the context of a multithreaded processor that supports renaming. A mapping unit may have a plurality of entries, each of which stores rename information for a dedicated one of a set of physical registers available to the processor for renaming. This physically-indexed mapping unit may support multiple threads, and may comprise a content-addressable memory (CAM) in certain embodiments. The mapping unit may support various combinations of read operations (to determine if a logical register is mapped to a physical register), write operations (to create or modify one or more entries containing mapping information), thread flush operations, and commit operations. More than one of such operations may be performed substantially simultaneously in certain embodiments.

摘要翻译： 这里描述了技术和系统以维持逻辑到物理寄存器的映射，例如在支持重命名的多线程处理器的上下文中。 映射单元可以具有多个条目，每个条目存储用于处理器可用于重命名的一组物理寄存器中的专用的一个的重命名信息。 该物理索引映射单元可以支持多个线程，并且在某些实施例中可以包括内容寻址存储器（CAM）。 映射单元可以支持读取操作的各种组合（以确定逻辑寄存器是否映射到物理寄存器），写入操作（用于创建或修改包含映射信息的一个或多个条目），线程刷新操作和提交操作。 在某些实施例中，可以基本上同时执行多于一个这样的操作。

公开(公告)号：US07131034B2

公开(公告)日：2006-10-31

申请号：US10292329

申请日：2002-11-12

申请人： Nadeem N. Eleyan ,  Harsh D. Sharma ,  Howard L. Levy ,  Hong S. Kim

发明人： Nadeem N. Eleyan ,  Harsh D. Sharma ,  Howard L. Levy ,  Hong S. Kim

IPC分类号： G06F11/00

CPC分类号： G01R31/31725 ,  H03K5/26 ,  H03K2005/00058 ,  H03K2005/00156

摘要： A signal duration measurement system compares a known duration, T1, of a test data signal with the duration, T2, of a state of a signal under test. In one embodiment, if T2 compares favorably with T1, then the circuit generating the signal under test ‘passes.’ Otherwise the signal under test ‘fails,’ and a problem has been identified. Furthermore, in one embodiment, T1 can be selectively adjusted to more accurately measure T2. In one embodiment, the test data signal is allowed to travel a signal path, having a known signal propagation delay time, during a single state of the signal under test. The data signal at the beginning of the state, e.g. during the rise of the signal under test, is compared to the data signal captured at the end of the state, e.g. during the fall of the signal under test. If the initial and captured data signals are the same, then the duration of the state of the signal under test is greater than or equal to the signal propagation delay time. The signal propagation time can be adjusted by inserting varying delay elements into the signal path traversed by test data signal. The signal duration measurement system can be fabricated on-chip, thus making its use more practical. The signal duration measurement system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure.

摘要翻译： 信号持续时间测量系统将测试数据信号的已知持续时间T 1与被测信号的状态的持续时间T 2进行比较。 在一个实施例中，如果T 2与T 1相比较好，则产生被测信号的电路“通过”。 否则被测信号“失败”，并且已经确定了一个问题。 此外，在一个实施例中，可以选择性地调整T 1以更准确地测量T 2。在一个实施例中，允许测试数据信号在信号的单个状态期间行进具有已知信号传播延迟时间的信号路径 被测试。 状态开始时的数据信号，例如， 在被测信号的上升期间，与在状态结束时捕获的数据信号进行比较。 在被测信号的坠落期间。 如果初始和捕获的数据信号相同，则被测信号的持续时间大于或等于信号传播延迟时间。 可以通过将变化的延迟元件插入由测试数据信号穿过的信号路径来调节信号传播时间。 信号持续时间测量系统可以片上制造，从而使其使用更加实用。 信号持续时间测量系统例如可用于测量难以外部测量的诸如自复位信号的信号的状态持续时间。

公开(公告)号：US06891403B2

公开(公告)日：2005-05-10

申请号：US10277566

申请日：2002-10-22

申请人： Harsh D. Sharma ,  Howard L. Levy ,  Hong Kim ,  Nadeem N. Eleyan

发明人： Harsh D. Sharma ,  Howard L. Levy ,  Hong Kim ,  Nadeem N. Eleyan

IPC分类号： G01R31/28 ,  H03L7/06 ,  G01R23/02

CPC分类号： H03L7/06 ,  G01R31/2882

摘要： The locked frequency of a PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determine whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal matches the jitter in the locked frequency of the PLL, the respective delay of the test-signal is used to determine the effective locked frequency of the PLL.

摘要翻译： PLL的锁定频率用于通过各种锁存器件（触发器等）来锁存测试信号。 各种不同的延迟被选择性地应用于测试信号以提供延迟的测试信号，并且测量延迟的测试信号以确定测试信号中的延迟是否与PLL的锁定频率中的抖动相匹配。 当测试信号的延迟与PLL的锁定频率中的抖动匹配时，测试信号的相应延迟用于确定PLL的有效锁定频率。

公开(公告)号：US08335912B2

公开(公告)日：2012-12-18

申请号：US12428461

申请日：2009-04-22

申请人： Robert T. Golla ,  Jama I. Barreh ,  Jeffrey S. Brooks ,  Howard L. Levy

发明人： Robert T. Golla ,  Jama I. Barreh ,  Jeffrey S. Brooks ,  Howard L. Levy

IPC分类号： G06F9/30 ,  G06F9/00

CPC分类号： G06F9/30109 ,  G06F9/384

摘要： Techniques and structures are described which allow the detection of certain dependency conditions, including evil twin conditions, during the execution of computer instructions. Information used to detect dependencies may be stored in a logical map table, which may include a content-addressable memory. The logical map table may maintain a logical register to physical register mapping, including entries dedicated to physical registers available as rename registers. In one embodiment, each entry in the logical map table includes a first value usable to indicate whether only a portion of the physical register is valid and whether the physical register includes the most recent update to the logical register being renamed. Use of this first value may allow precise detection of dependency conditions, including evil twin conditions, upon an instruction reading from at least two portions of a logical register having an entry in the logical map table whose first value is set.

摘要翻译： 描述了在执行计算机指令期间允许检测某些依赖条件（包括恶性条件）的技术和结构。 用于检测依赖性的信息可以存储在逻辑映射表中，逻辑映射表可以包括可内容寻址的存储器。 逻辑映射表可以将逻辑寄存器保持为物理寄存器映射，包括专用于可用作重命名寄存器的物理寄存器的条目。 在一个实施例中，逻辑映射表中的每个条目包括可用于指示仅一部分物理寄存器是否有效的第一值以及该物理寄存器是否包括对重命名的逻辑寄存器的最新更新。 当从逻辑寄存器的至少两个部分读取逻辑映射表中具有第一个值的条目的指令读取时，使用该第一个值可以允许精确地检测依赖条件，包括恶性条件。

公开(公告)号：US20100274993A1

公开(公告)日：2010-10-28

申请号：US12428461

申请日：2009-04-22

申请人： Robert T. Golla ,  Jama I. Barreh ,  Jeffrey S. Brooks ,  Howard L. Levy

发明人： Robert T. Golla ,  Jama I. Barreh ,  Jeffrey S. Brooks ,  Howard L. Levy

IPC分类号： G06F9/30

CPC分类号： G06F9/30109 ,  G06F9/384

摘要： Techniques and structures are described which allow the detection of certain dependency conditions, including evil twin conditions, during the execution of computer instructions. Information used to detect dependencies may be stored in a logical map table, which may include a content-addressable memory. The logical map table may maintain a logical register to physical register mapping, including entries dedicated to physical registers available as rename registers. In one embodiment, each entry in the logical map table includes a first value usable to indicate whether only a portion of the physical register is valid and whether the physical register includes the most recent update to the logical register being renamed. Use of this first value may allow precise detection of dependency conditions, including evil twin conditions, upon an instruction reading from at least two portions of a logical register having an entry in the logical map table whose first value is set.

摘要翻译： 描述了在执行计算机指令期间允许检测某些依赖条件（包括恶性条件）的技术和结构。 用于检测依赖性的信息可以存储在逻辑映射表中，逻辑映射表可以包括可内容寻址的存储器。 逻辑映射表可以将逻辑寄存器保持为物理寄存器映射，包括专用于可用作重命名寄存器的物理寄存器的条目。 在一个实施例中，逻辑映射表中的每个条目包括可用于指示仅一部分物理寄存器是否有效的第一值以及该物理寄存器是否包括对重命名的逻辑寄存器的最新更新。 当从逻辑寄存器的至少两个部分读取逻辑映射表中具有第一个值的条目的指令读取时，使用该第一个值可以允许精确地检测依赖条件，包括恶性条件。

公开(公告)号：US07036098B2

公开(公告)日：2006-04-25

申请号：US10610252

申请日：2003-06-30

申请人： Nadeem N. Eleyan ,  Harsh D. Sharma ,  Howard L. Levy ,  Hong S. Kim

发明人： Nadeem N. Eleyan ,  Harsh D. Sharma ,  Howard L. Levy ,  Hong S. Kim

IPC分类号： G06F17/50

CPC分类号： H03K5/04 ,  G01R31/3016 ,  G01R31/31725

摘要： Signal state durations, such as the pulse-width, of on-chip signals are often critical to the successful operation of an integrated circuit. The signal state durations measured by on-chip technology provide signal state duration information to an on-chip signal state duration control system. The signal state duration control system uses the information to adjust the signal state duration of an on-chip signal. In one embodiment, the signal state duration of the on-chip signal is the pulse width of the on-chip signal. The signal duration measurement and adjustment system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure and adjust signal state durations using on-chip technology.

摘要翻译： 片上信号的信号状态持续时间（如脉冲宽度）通常对集成电路的成功运行至关重要。 通过片上技术测量的信号状态持续时间将信号状态持续时间信息提供给片上信号状态持续时间控制系统。 信号状态持续时间控制系统使用信息来调整片上信号的信号状态持续时间。 在一个实施例中，片上信号的信号状态持续时间是片上信号的脉冲宽度。 信号持续时间测量和调整系统例如可用于测量诸如自复位信号的状态持续时间，这些信号难以外部测量并使用片上技术来调整信号状态持续时间。

公开(公告)号：US07085176B1

公开(公告)日：2006-08-01

申请号：US10771526

申请日：2004-02-04

申请人： Howard L. Levy ,  Nadeem N. Eleyan ,  Nayon Tomsio ,  Hong S. Kim

发明人： Howard L. Levy ,  Nadeem N. Eleyan ,  Nayon Tomsio ,  Hong S. Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/20

摘要： It has been discovered that initialization of a memory array can be improved by setting the nodes of the memory array to a predetermined value automatically upon applying power to the integrated circuit. Data input nodes and a memory write enable node are configured to store the predetermined values on the nodes of the memory array in response to successive enablement of word lines corresponding to the nodes of the memory array and automatic reset of the word lines. Circuitry included for initializing control and data signals of the memory array are effectively disabled upon termination of the initialization. Inclusion of circuitry that initiates and terminates the initialization obviates an additional input/output pin for this purpose.

摘要翻译： 已经发现，通过在对集成电路施加电力时将存储器阵列的节点自动设置为预定值，可以提高存储器阵列的初始化。 数据输入节点和存储器写使能节点被配置为响应于对应于存储器阵列的节点的字线的连续启用和字线的自动复位，将预定值存储在存储器阵列的节点上。 包括用于初始化存储器阵列的控制和数据信号的电路在初始化结束时被有效禁止。 启动和终止初始化的电路的包含为此避免了额外的输入/输出引脚。