公开(公告)号：US07288827B2

公开(公告)日：2007-10-30

申请号：US10969718

申请日：2004-10-20

申请人： Huajie Chen ,  Kathryn T. Schonenberg ,  Gregory G. Freeman ,  Andreas D. Stricker ,  Jae-Sung Rieh

发明人： Huajie Chen ,  Kathryn T. Schonenberg ,  Gregory G. Freeman ,  Andreas D. Stricker ,  Jae-Sung Rieh

IPC分类号： H01L27/082 ,  H01L27/102

CPC分类号： H01L29/66242 ,  H01L21/32105 ,  Y10S438/911

摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.

摘要翻译： 使用不同材料的不同氧化速率形成自对准氧化物掩模。 自对准氧化物掩模形成在CVD生长的基底NPN基层上，其牺牲了场上的活性区域上的单晶Si（或Si / SiGe）和多晶Si（或Si / SiGe）。 通过利用多晶硅（或Si / SiGe）比单晶Si（或Si / SiGe）更快地氧化的事实来制造自对准掩模。 通过使用热氧化工艺在多晶硅（或Si / siGe）和单晶Si（或Si / siGe）上形成氧化膜，以在多晶硅（或Si / SiGe）上形成厚的氧化层，以及 在单晶Si（或Si / siGe）上方的薄氧化层，随后进行受控氧化物蚀刻以除去单晶Si（或Si / siGe）上的薄氧化层，同时将自对准氧化物掩模层留在 多晶硅（或Si / siGe）。 然后在自对准掩模形成之后形成隆起的外在基体。 该自对准氧化物掩模阻挡从扩展的外在碱基到收集器角的扩散。

公开(公告)号：US06844225B2

公开(公告)日：2005-01-18

申请号：US10345469

申请日：2003-01-15

申请人： Huajie Chen ,  Kathryn T. Schonenberg ,  Gregory G. Freeman ,  Andreas D. Stricker ,  Jae-Sung Rieh

发明人： Huajie Chen ,  Kathryn T. Schonenberg ,  Gregory G. Freeman ,  Andreas D. Stricker ,  Jae-Sung Rieh

IPC分类号： H01L21/321 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L21/00

CPC分类号： H01L29/66242 ,  H01L21/32105 ,  Y10S438/911

摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.

摘要翻译： 使用不同材料的不同氧化速率形成自对准氧化物掩模。 自对准氧化物掩模形成在CVD生长的基底NPN基层上，其牺牲了场上的活性区域上的单晶Si（或Si / SiGe）和多晶Si（或Si / SiGe）。 通过利用多晶硅（或Si / SiGe）比单晶Si（或Si / SiGe）更快地氧化的事实来制造自对准掩模。 通过使用热氧化工艺在多晶硅（或Si / siGe）和单晶Si（或Si / siGe）上形成氧化膜，以在多晶硅（或Si / SiGe）上形成厚的氧化层，以及 在单晶Si（或Si / siGe）上方的薄氧化层，随后进行受控氧化物蚀刻以除去单晶Si（或Si / siGe）上的薄氧化层，同时将自对准氧化物掩模层留在 多晶硅（或Si / siGe）。 然后在自对准掩模形成之后形成隆起的外在基体。 该自对准氧化物掩模阻挡从扩展的外在碱基到收集器角的扩散。

公开(公告)号：US07442595B2

公开(公告)日：2008-10-28

申请号：US11511047

申请日：2006-08-28

申请人： Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg ,  Andreas D. Stricker

发明人： Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg ,  Andreas D. Stricker

IPC分类号： H01L21/337

CPC分类号： H01L29/66068 ,  H01L29/2003 ,  H01L29/66242

摘要： A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.

摘要翻译： 提供了通过不包括C离子注入的方法将C并入到异质结双极器件的集电极区域中的结构和方法。 在本发明中，通过在刻蚀到集电极区域的周边沟槽中外延生长将C引入集电体，以更好地控制碳分布和位置。 通过使用沟槽隔离区域将集电极区域和在集电体的中心部分上的图案化层作为掩模来形成沟槽。 然后，使用沟槽内部的选择性外延生长Si：C以形成具有清晰且明确界定的边缘的Si：C区域。 可以优化深度，宽度和C含量以控制和定制集电极注入扩散并减少寄生C CB的周边分量。

公开(公告)号：US07170083B2

公开(公告)日：2007-01-30

申请号：US10905510

申请日：2005-01-07

申请人： Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg ,  Andreas D Stricker

发明人： Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg ,  Andreas D Stricker

IPC分类号： H01L29/06

CPC分类号： H01L29/66068 ,  H01L29/2003 ,  H01L29/66242

摘要： A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.

摘要翻译： 提供了通过不包括C离子注入的方法将C并入到异质结双极器件的集电极区域中的结构和方法。 在本发明中，通过在刻蚀到集电极区域的周边沟槽中外延生长将C引入集电体，以更好地控制碳分布和位置。 通过使用沟槽隔离区域将集电极区域和在集电体的中心部分上的图案化层作为掩模来形成沟槽。 然后，使用沟槽内部的选择性外延生长Si：C以形成具有清晰且明确界定的边缘的Si：C区域。 可以优化深度，宽度和C含量以控制和定制集电极注入扩散并减少寄生C CB的周边分量。

公开(公告)号：US06780695B1

公开(公告)日：2004-08-24

申请号：US10249563

申请日：2003-04-18

申请人： Huajie Chen ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Gregory G. Freeman ,  David C. Ahlgren ,  David Angell ,  Kathryn T. Schonenberg ,  Kenneth J. Stein ,  Fen F. Jamin

发明人： Huajie Chen ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Gregory G. Freeman ,  David C. Ahlgren ,  David Angell ,  Kathryn T. Schonenberg ,  Kenneth J. Stein ,  Fen F. Jamin

IPC分类号： H01L218238

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area. At least one bipolar transistor having a raised extrinsic base is then formed in the at least one opening.

摘要翻译： 提供一种形成具有凸起的外在基极的BiCMOS集成电路的方法。 该方法包括首先在位于具有用于形成至少一个双极晶体管的器件区域的衬底的顶部的栅极电介质的表面上方形成多晶硅层，以及用于形成至少一个互补金属氧化物半导体（CMOS）晶体管的器件区域）。 然后将多晶硅层图案化以在器件区域上提供用于形成至少一个双极晶体管及其周围区域的牺牲多晶硅层，同时在用于形成至少一个CMOS晶体管的器件区域中提供至少一个栅极导体。 然后围绕至少一个栅极导体的每一个形成至少一对间隔物，然后选择性地去除双极器件区域上的牺牲多晶硅层的一部分以在双极器件区域中提供至少一个开口。 然后在至少一个开口中形成至少一个具有凸起的非本征基极的双极晶体管。

公开(公告)号：US06927476B2

公开(公告)日：2005-08-09

申请号：US09962738

申请日：2001-09-25

申请人： Gregory G. Freeman ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Kathryn T. Schonenberg ,  Shwu-Jen Jeng ,  Kenneth J. Stein ,  Jeffrey B. Johnson

发明人： Gregory G. Freeman ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Kathryn T. Schonenberg ,  Shwu-Jen Jeng ,  Kenneth J. Stein ,  Jeffrey B. Johnson

IPC分类号： H01L21/331 ,  H01L29/10 ,  H01L29/737 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

摘要： A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing. The heterojunction bipolar transistor simultaneously improves three factors that affect the speed and performance of bipolar transistors: base width, base resistance, and base-collector capacitance.

摘要翻译： 本文公开了一种凸起的外在基极，硅锗（SiGe）异质结双极晶体管（HBT）及其制造方法。 异质结双极晶体管包括基板，形成在基板上的硅锗层，形成在基板上的集电极层，形成在硅锗层上的升高的非本征基极层和形成在硅锗层上的发射极层。 硅锗层在发射极层和凸起的非本征基极层之间形成异质结。 双极晶体管还包括形成在凸起的非本征基极层的一部分上的基极，在集电极层的一部分上形成的集电极，以及形成在发射极层的一部分上的发射极。 因此，异质结双极晶体管包括自对准凸起的外在基极，最小结深度以及影响基底宽度的最小间隙缺陷，全部以最小的热处理形成。 异质结双极晶体管同时改善了影响双极晶体管速度和性能的三个因素：基极宽度，基极电阻和基极集电极电容。

公开(公告)号：US06803642B2

公开(公告)日：2004-10-12

申请号：US10008383

申请日：2001-12-06

申请人： Gregory G. Freeman ,  Jae-Sung Rieh

发明人： Gregory G. Freeman ,  Jae-Sung Rieh

IPC分类号： H01L21331

CPC分类号： H01L29/66242 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/7378

摘要： A non-uniform depth base-emitter junction, with deeper junction at the lateral portions of the emitter, preferably coupled with a recessed and raised extrinsic base, bipolar transistor, and a method of making the same. The bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a recessed and raised extrinsic base layer formed on the silicon germanium layer, and a silicon pedestal on which an emitter layer is formed. The emitter has non-uniform depths into the base layer.

摘要翻译： 不均匀的深度基极 - 发射极结，其在发射极的侧部具有更深的结，优选地与凹陷和凸起的非本征基极双极晶体管耦合，以及制造它们的方法。 双极晶体管包括基板，形成在基板上的硅锗层，形成在基板上的集电极层，形成在硅锗层上的凹凸凸起的非本征基极层以及形成有发射极层的硅基座。 发射器具有不均匀的深度进入基层。

公开(公告)号：US20080128861A1

公开(公告)日：2008-06-05

申请号：US11555906

申请日：2006-11-02

申请人： Omer H. Dokumaci ,  Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

发明人： Omer H. Dokumaci ,  Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

IPC分类号： H01L29/73

CPC分类号： H01L29/7378 ,  H01L29/0821 ,  H01L29/66242

摘要： Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.

摘要翻译： 提供双极晶体管，特别是SiGe异质结双极晶体管的性能的方法与通过本发明方法形成的结构一起提供。 所述方法包括向至少一个收集器提供包含C，惰性气体或其混合物的富含物质的掺杂剂区域。 富含物质的掺杂剂区域围绕收集器的中心部分形成周边或环形掺杂剂区域。 然后将第一导电型掺杂剂注入到集电极的中心部分中，以形成由外部富物质掺杂区域横向约束，即限制的第一导电型掺杂剂区域。

公开(公告)号：US07476914B2

公开(公告)日：2009-01-13

申请号：US11555906

申请日：2006-11-02

申请人： Omer H. Dokumaci ,  Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

发明人： Omer H. Dokumaci ,  Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

IPC分类号： H01L21/331

CPC分类号： H01L29/7378 ,  H01L29/0821 ,  H01L29/66242

摘要： Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.

摘要翻译： 提供双极晶体管，特别是SiGe异质结双极晶体管的性能的方法与通过本发明方法形成的结构一起提供。 所述方法包括向至少一个收集器提供包含C，惰性气体或其混合物的富含物质的掺杂剂区域。 富含物质的掺杂剂区域围绕收集器的中心部分形成周边或环形掺杂剂区域。 然后将第一导电型掺杂剂注入到集电极的中心部分中，以形成由外部富物质掺杂区域横向约束，即限制的第一导电型掺杂剂区域。

公开(公告)号：US07144787B2

公开(公告)日：2006-12-05

申请号：US10908363

申请日：2005-05-09

申请人： Omer H. Dokumaci ,  Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

发明人： Omer H. Dokumaci ,  Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

IPC分类号： H01L21/331

CPC分类号： H01L29/7378 ,  H01L29/0821 ,  H01L29/66242

摘要： Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.